"What can be more palpably absurd than the prospect held out of locomotives traveling twice as fast as stagecoaches?"
The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 7439579 | Power semiconductor with functional element guide structure A trench transistor is described. In one aspect, the trench transistor has a cell array having a plurality of cell array trenches and a plurality of mesa zones arranged between the cell array trenches, and a semiconductor functional element formed in one of the mesa... | 10/21/2008 |
| 7385248 | Shielded gate field effect transistor with improved inter-poly dielectric A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insul... | 06/10/2008 |
| 7285455 | Method of producing the same A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor. | 10/23/2007 |
| 7183600 | Semiconductor device with trench gate type transistor and method of manufacturing the same A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other i... | 02/27/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7118971 | Method for fabricating trench power device Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay.... | 10/10/2006 |
| 6646304 | Universal semiconductor wafer for high-voltage semiconductor components A universal semiconductor wafer for high-voltage semiconductor components includes at least one layer of a first conductivity type which is provided on a semiconductor substrate of the first conductivity type. A plurality of floating semiconductor zones o... | 11/11/2003 |
| 6642120 | Semiconductor circuit A semiconductor circuit is provided which has a high breakdown voltage and is capable of outputting a large current. Field transistors (Q1, Q11) are cross-coupled. The gate of the first field transistor (Q1) and the drain of the second field transistor (Q... | 11/04/2003 |
| 6630711 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 10/07/2003 |
| 6541818 | Field-effect transistor configuration with a trench-shaped gate electrode and an additional highly doped layer in the body region A field effect transistor configuration with a trench gate electrode and a method for producing the same. An additional highly doped layer is provided in the body region under the source. The layer is used for influencing the conductibility of the source ... | 04/01/2003 |
| 6534830 | Low impedance VDMOS semiconductor component A low impedance VDMOS semiconductor component having a planar gate structure is described. The VDMOS semiconductor component contains a semiconductor body of a first conductivity type having two main surfaces, including a first main surface and a second m... | 03/18/2003 |
| 6437399 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 08/20/2002 |
| 6225649 | Insulated-gate bipolar semiconductor device An insulated-gate bipolar semiconductor device is provided wherein electric resistance generated in an emitter impurity region and between an emitter electrode and a region in the close vicinity of a gate takes a prescribe value irrespective of the distan... | 05/01/2001 |
| 6184555 | Field effect-controlled semiconductor component The invention relates to a field effect-controllable semiconductor component of vertical or lateral design i.e. MOSFETs and IGBTs. In this case, depletion zones and complementary depletion zones of opposite conduction types are introduced in the source-dr... | 02/06/2001 |
| 6150694 | Silicon-on-insulator insulated gate bipolar transistor A silicon-on-insulator insulated gate bipolar transistor (SOI-IGBT) has a channel zone of a first conductivity type, at least one cell zone of a second conductivity type, and at least one intermediate zone of the first conductivity type which delimits the... | 11/21/2000 |
| 6144065 | MOS gated device with self aligned cells An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical ali... | 11/07/2000 |
| 6110799 | Trench contact process A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into... | 08/29/2000 |
| 6091107 | Semiconductor devices An Insulated Gate Bipolar Transistor has a gate in the form of a trench positioned in a p region in a silicon body. The device operates in a thyristor mode having a virtual emitter which is formed during operation by the generation of an inversion layer a... | 07/18/2000 |
| 6084284 | Integrated circuit including inverted dielectric isolation A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bondin... | 07/04/2000 |
| 6054748 | High voltage semiconductor power device A semiconductor power device includes a high-resistance semiconductor substrate of the first conductivity type having first and second major surfaces and a recess in either one of the first and second major surfaces, and a semiconductor power element with... | 04/25/2000 |
| 6037628 | Semiconductor structures with trench contacts Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pi... | 03/14/2000 |
| 5981981 | Semiconductor device including a bipolar structure A high concentration n-type semiconductor region (21) having a width (W) and a distance (D) of constant ranges is selectively formed to be overlapped with or adjacent to a buffer layer (2). When a thickness (L) of an n-type semiconductor layer (3) is 50 Î... | 11/09/1999 |
| 5910668 | Method of making a insulated gate bipolar transistor with high-energy P+ implant and silicon-etch contact An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a ... | 06/08/1999 |
| 5909039 | Insulated gate bipolar transistor having a trench An IGBT comprises a drain, a highly doped p-type substrate layer, a highly doped n-type buffer layer, a drift layer, a p-type base layer, a highly doped n-type source region layer and a source electrode. A trench is etched in the base layer and an insulat... | 06/01/1999 |
| 5894154 | P-channel MOS transistor The specification describes a p-channel MOS with self-aligned source and drain, and fabricated by a process that is fully compatible with simultaneously forming complementary self-aligned n-channel MOS devices and complementary IGBT devices.... | 04/13/1999 |
| 5891776 | Methods of forming insulated-gate semiconductor devices using self-aligned trench sidewall diffusion techniques A method of forming an insulated gate semiconductor device includes the steps of patterning an insulated gate electrode on a face of a substrate containing a first conductivity type region and forming a trench at the face using the gate electrode as a mas... | 04/06/1999 |
| 5879968 | Process for manufacture of a P-channel MOS gated device with base implant through the contact window An MOS-gated power semiconductor device is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body or channel region and the source region of ... | 03/09/1999 |
| 5869864 | Field effect controlled semiconductor component A semiconductor component having a body with an upper surface, a base zone having a portion adjoining the upper surface of the semiconductor body, at least one source zone embedded in the base zone, at least one gate electrode lying parallel to the upper ... | 02/09/1999 |
| 5843796 | Method of making an insulated gate bipolar transistor with high-energy P+ i m An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a ... | 12/01/1998 |
| 5841197 | Inverted dielectric isolation process A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bondin... | 11/24/1998 |
| 5804483 | Method for producing a channel region layer in a sic-layer for a voltage controlled semiconductor device In a method for producing a channel region layer in a SiC-layer for producing a voltage controlled semiconductor device n-type dopants and p-type dopants are implanted into a near-surface layer of the SiC layer. The p-type dopants implanted have a higher ... | 09/08/1998 |
| 5801417 | Self-aligned power MOSFET device with recessed gate and source A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed a... | 09/01/1998 |
| 5795793 | Process for manufacture of MOS gated device with reduced mask count A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask to sequentially form a cell body and a source region within the cell body, and a second mask step to form, by a silicon etch, a central opening in the silicon s... | 08/18/1998 |
| 5763902 | Insulated gate bipolar transistor having a trench and a method for production thereof An insulated gate bipolar transistor comprises a drain which supports a highly doped p-type substrate layer; a low doped n-type drift layer supported over the substrate layer; a base layer supported over the drift layer including a trench extending into t... | 06/09/1998 |
| 5731604 | Semiconductor device MOS gated A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask to sequentially form a cell body and a source region within the cell body, and a second mask step to form, by a silicon etch, a central opening in the silicon s... | 03/24/1998 |
| 5728593 | Power insulated-gate transistor having three terminals and a manufacturing method thereof The present invention relates to a method of manufacturing an insulated-gate transistor including a very thin P- layer as a channel under a gate terminal. The device and method differs from conventional devices and techniques in that the P | 03/17/1998 |
| 5703384 | MOS semiconductor component having improved transmission properties In IGBTs or, respectively, MOSFETs a parasitic junction-FET effect can be nearly avoided on the basis of an insulation layer introduced between the two base zones and into which an electrode is additionally embedded. The on-resistance is lowered as a resu... | 12/30/1997 |
| 5663079 | Method of making increased density MOS-gated semiconductor devices In a method of fabricating semiconductor devices such as transistors and in the devices formed thereby, a doped polysilicon layer is formed overlying an insulated gate. The doped polysilicon layer extends over the top and the sidewalls of the gate to cont... | 09/02/1997 |
| 5623152 | Insulated gate semiconductor device An insulated gate semiconductor device includes a gate trench having a gate electrode formed therein on a gate insulating film, and an emitter trench having an emitter electrode formed therein on a silicon oxide layer, to form a capacitance of a capacitor... | 04/22/1997 |
| 5583060 | Method for manufacturing field effect controlled semiconductor components The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the de... | 12/10/1996 |