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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7405435 | Semiconductor device having electrostatic destruction protection circuit using thyristor as protection element A semiconductor device includes a thyristor, trigger circuit and surge detection/leakage reduction circuit. The anode of the thyristor is connected to a first terminal and the cathode thereof is connected to a second terminal. The trigger circuit is configured to fi... | 07/29/2008 |
| 6558996 | Edge structure for relaxing electric field of semiconductor device having an embedded type diffusion structure Plural p+ -type regions are formed on a silicon substrate, and thereafter, an n-type epitaxial growth layer is formed. Narrow concave portions are formed to extend between the surface of the epitaxial growth layer 14 and the silicon substrate a... | 05/06/2003 |
| 6465871 | Semiconductor switching device and method of controlling a carrier lifetime in a semiconductor switching device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semi... | 10/15/2002 |
| 6426521 | Semiconductor device In a semiconductor device of self-extinguish type, in which a channel constituting a current path is controlled by a control voltage applied to a gate electrode, the channel is constructed between an n type cathode region 12 formed in one major surface of... | 07/30/2002 |
| 6423986 | Field-controlled high-power semiconductor devices Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer (60). A semiconductor layer junction, remote from both... | 07/23/2002 |
| 6396126 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/28/2002 |
| 6291304 | Method of fabricating a high voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device)d a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 09/18/2001 |
| 6285046 | Controllable semiconductor structure with improved switching properties The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the sourc... | 09/04/2001 |
| 6252259 | Semiconductor switching device having different carrier lifetimes between a first portion serving as a main current path and the remaining portion of the device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is uniform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semico... | 06/26/2001 |
| 6180959 | Static induction semiconductor device, and driving method and drive circuit thereof In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source re... | 01/30/2001 |
| 6180965 | Semiconductor device having a static induction in a recessed portion In a static induction semiconductor device, particular a high power static induction semiconductor device, recessed portions 12 are formed in one surface of a silicon substrate 11 of one conductivity type, gate regions 13 of the other conductivity type ar... | 01/30/2001 |
| 6159776 | Method for manufacturing semiconductor device A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P+ layer in a lower surface of an N- substrate, selectively forming P+ gate regions in an upper surface of... | 12/12/2000 |
| 6107649 | Field-controlled high-power semiconductor devices Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. A layer of the top surface forms a control layer. A semiconductor layer junction, remote from top and bo... | 08/22/2000 |
| 6011279 | Silicon carbide field controlled bipolar switch A field controlled bipolar switch having a bulk single crystal silicon carbide substrate of a first conductivity type having an upper surface and a lower surface. A first epitaxial layer of a second conductivity type silicon carbide is formed upon the upp... | 01/04/2000 |
| 5956577 | Method of manufacturing serrated gate-type or joined structure A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to ... | 09/21/1999 |
| 5950075 | Semiconductor device having recessed gate regions and method of manufacturing the same In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate... | 09/07/1999 |
| 5946572 | Method of manufacturing a semiconductor device having recessed gate structures A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is b... | 08/31/1999 |
| 5930651 | Method of forming a semiconductor device having a plurality of cavity defined gating regions A P+ layer is formed on the lower surface of an N- substrate, and recesses are defined in the upper surface of the N- substrate. Then, P+ gate regions and bottom gate regions are formed in side walls and bot... | 07/27/1999 |
| 5917204 | Insulated gate bipolar transistor with reduced electric fields AN IGBT including a collector positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertic... | 06/29/1999 |
| 5894140 | Semiconductor device having recessed gate structures and method of manufacturing the same A gate structure including semiconductor regions each having a high impurity-concentration and being formed within respective one of recessed portions provided in a surface of a first semiconductor substrate, and then a second semiconductor substrate is b... | 04/13/1999 |
| 5847417 | Semiconductor device and method of manufacturing same A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P+ layer in a lower surface of an N- substrate, selectively forming P+ gate regions in an upper surface of... | 12/08/1998 |
| 5841155 | Semiconductor device containing two joined substrates A method of manufacturing a joined-type semiconductor device having a gate structure. The semiconductor device includes a first and second semiconductor substrates each having a substrate body, and a first and a second main surfaces which are opposite to ... | 11/24/1998 |
| 5773868 | Semiconductor device and method of manufacturing the same A semiconductor device having a dielectric isolation (DI) structure using an SOI substrate or the like. An active region as a main current path of the semiconductor device is sandwiched between DI grooves having a side wall substantially vertical to the m... | 06/30/1998 |
| 5757035 | Semiconductor device In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate... | 05/26/1998 |
| 5753938 | Static-induction transistors having heterojunction gates and methods of forming same A semiconductor switching device includes a plurality of adjacent heterojunction-gate static-induction transistor (SIT) unit cells connected in parallel in a monocrystalline silicon carbide substrate having first and second opposing faces, a relatively hi... | 05/19/1998 |
| 5702962 | Fabrication process for a static induction transistor A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N-... | 12/30/1997 |
| 5665988 | Conductivity-modulation semiconductor A plurality of minority carriers, which cause a conductivity modulation effect in a semiconductor device, are supplied from a separately disposed minority carrier injection region which is alternately connected to and separated from a drain region. The mi... | 09/09/1997 |
| 5665987 | Insulated gate static induction thyristor with a split gate type shorted cathode structure In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed in the second gate. A MOS structure is forme... | 09/09/1997 |
| 5648665 | Semiconductor device having a plurality of cavity defined gating regions and a fabrication method therefor A P+ layer is formed on the lower surface of an N- substrate, and recesses are defined in the upper surface of the N- substrate. Then, P+ gate regions and bottom gate regions are formed in side walls and bot... | 07/15/1997 |
| 5602405 | Semiconductor device with base formed by the junction of two semiconductors of the same conductive type A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N-... | 02/11/1997 |
| 5545905 | Static induction semiconductor device with a static induction schottky shorted structure The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main e... | 08/13/1996 |
| 5510274 | Method of controlling a carrier lifetime in a semiconductor switching device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semi... | 04/23/1996 |
| 5489788 | Insulated gate semiconductor device with improved short-circuit tolerance In an insulated gate semiconductor device, a loss is suppressed and a short-circuit tolerance as well as a latch-up tolerance are improved. A saturation current ICE (sat) and a short-circuit tolerance tw are reduced without much influencing a c... | 02/06/1996 |
| 5461242 | Insulated gate static induction thyristor with a split gate type shorted cathode structure In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate region of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed between the first and second gate reg... | 10/24/1995 |
| 5444271 | Conductivity-modulated semiconductor device with high breakdown voltage Base regions of a second conductivity type are formed and spaced apart from one another in a first major surface of a semiconductor substrate of a first conductivity type which functions as a drain region. Source regions of the first conductivity type are... | 08/22/1995 |
| 5426314 | Insulated gate control static induction thyristor A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semico... | 06/20/1995 |
| 5418376 | Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure The present invention is to provide a static induction semiconductor device with a distributed main electrode structure and a static induction semiconductor device with a static induction main electrode shorted structure where the main electrode region is... | 05/23/1995 |
| 5391897 | Status induction semiconductor device A static induction semiconductor device has a low-resistance drain region, a high-resistance layer disposed on the drain region, a low-resistance source region spaced from the high-resistance layer, a low-resistance gate region disposed in the high-resist... | 02/21/1995 |
| 5378911 | Structure of semiconductor device A structure of a semiconductor device according to the present invention has a normally-off characteristic, a well controlability, a very low on-resistance, a capability for a high breakdown voltage, and is free from parasitic devices. For example, said s... | 01/03/1995 |
| 5359220 | Hybrid bipolar/field-effect power transistor in group III-V material system A hybrid power transistor (40) includes a vertical PNP bipolar transistor (42) having a floating base (46). A junction-gate type field-effect transistor (FET) (62) has a lateral N-type channel (64,66) and a vertical electron injection path (54) from the c... | 10/25/1994 |
