Class 257/E29.193 - Comprising lattice mismatched active layers (e.g., SiGe strained layer transistors) (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.189. This subclass
No. of patents: 178
Last issue date: 10/28/2008

«First «Previous1 2 3 4 5 Next»Last»

Number	Title	Issue Date
7442967	Strained channel complementary field-effect transistors A transistor includes a gate dielectric overlying a channel region. A source region and a drain region are located on opposing sides of the channel region. The channel region is formed from a first semiconductor material and the source and drain regions are formed f...	10/28/2008
7432559	Silicide formation on SiGe A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and sili...	10/07/2008
7391047	System for forming a strained layer of semiconductor material A method for forming a strained layer of semiconductor material, e.g., silicon, germanium, Group III/V, silicon germanium alloy. The method includes providing a non-deformable surface region having a first predetermined radius of curvature, which is defined by R(1) ...	06/24/2008
7388267	Selective stress engineering for SRAM stability improvement An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained ...	06/17/2008
7364989	Strain control of epitaxial oxide films using virtual substrates A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy	04/29/2008
7351994	Noble high-k device At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one diele...	04/01/2008
7348284	Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the sil...	03/25/2008
7345299	Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon Enriched floating charge trapping media over the crystalline layer The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The sour...	03/18/2008
7339205	Gallium nitride materials and methods associated with the same Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between ...	03/04/2008
7335545	Control of strain in device layers by prevention of relaxation The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance. ...	02/26/2008
7326997	Method and structure for enhancing both nMOSFET and pMOSFET performance with a stressed film A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET dev...	02/05/2008
7323710	Fin field effect transistors having multi-layer fin patterns A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that...	01/29/2008
7307274	Transistors having reinforcement layer patterns and methods of forming the same According to some embodiments of the invention, there is provided line photo masks that includes transistors having reinforcement layer patterns and methods of forming the same. The transistors and the methods provide a way of compensating a partially removed amount...	12/11/2007
7307273	Control of strain in device layers by selective relaxation The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance. ...	12/11/2007
7285798	CMOS inverter constructions Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed ...	10/23/2007
7279700	Semiconductor substrate and process for producing it A semiconductor substrate useful as a donor wafer is a single-crystal silicon wafer having a relaxed, single-crystal layer containing silicon and germanium on its surface, the germanium content at the surface of the layer being in the range from 10% by weight to 100...	10/09/2007
7238985	Trench type mosgated device with strained layer on trench sidewall A MOSgated trench device has a reduced on resistance by forming a less than about a 13 nm thick strained SiGe layer on the silicon surface of the trenches and forming a thin (30 nm or less) layer of epitaxially deposited silicon on the SiGe layer which epi layer is ...	07/03/2007
7229892	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on...	06/12/2007
7230264	Semiconductor transistor having structural elements of differing materials A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a...	06/12/2007
7217949	Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate inc...	05/15/2007
7208754	Strained silicon structure A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the s...	04/24/2007
7202513	Stress engineering using dual pad nitride with selective SOI device architecture A method for engineering stress in the channels of MOS transistors of different conductivity using highly stressed nitride films in combination with selective semiconductor-on-insulator (SOI) device architecture is described. A method of using compressive and tensil...	04/10/2007
7183613	Method and structure for enhancing both NMOSFET and PMOSFET performance with a stressed film A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET dev...	02/27/2007
7163867	Method for slowing down dopant-enhanced diffusion in substrates and devices fabricated therefrom A method (and resulting structure) of forming a semiconductor device, includes implanting, on a substrate, a dopant and at least one species, annealing the substrate, the at least one species retarding a diffusion of the dopant during the annealing of the substrate....	01/16/2007
7164183	Semiconductor substrate, semiconductor device, and method of manufacturing the same A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress t...	01/16/2007
7161169	Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein ...	01/09/2007
7154118	Bulk non-planar transistor having strained enhanced mobility and methods of fabrication A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed o...	12/26/2006
7145169	Field-effect transistor, semiconductor device, and photo relay A field-effect transistor includes a silicon layer formed on an insulating film, a first-conductivity-type base and a second-conductivity-type source layers formed in the silicon layer being adjacent to each other, a second-conductivity-type drain layer formed in th...	12/05/2006
7129530	Semiconductor device A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitte...	10/31/2006
7129516	Ion recoil implantation and enhanced carrier mobility in CMOS device An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology ...	10/31/2006
7115945	Strained silicon fin structure Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing s...	10/03/2006
7109096	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device including: providing a substrate having an insulating layer and a single crystal silicon layer formed on the insulating layer; forming a strain-inducing semiconductor layer on the single crystal silicon layer, the str...	09/19/2006
7095043	Semiconductor device, semiconductor circuit module and manufacturing method of the same An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not f...	08/22/2006
6960781	Shallow trench isolation process A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor. ...	11/01/2005
6949761	Structure for and method of fabricating a high-mobility field-effect transistor A structure and method of fabricating a high-mobility semiconductor layer structure and field-effect transistor (MODFET) that includes a high-mobility conducting channel, while at the same time, maintaining counter doping to control deleterious short-channel effects...	09/27/2005
6855963	Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate A silicon and silicon germanium based semiconductor MODFET device design and method of manufacture. The MODFET design includes a high-mobility layer structure capable of ultra high-speed, low-noise for a variety of communication applications including RF, microwave,...	02/15/2005
6699741	Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are e...	03/02/2004
6699765	Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer...	03/02/2004
6680234	Semiconductor device having the effect that the drop in the current gain is kept to the minimum, when the substrate density is amplified and that the variation in the collector current is improved A semiconductor device includes a SiGe base bipolar transistor. The SiGe base bipolar transistor includes an emitter layer, a collector layer and a SiGe base layer formed of silicon containing germanium. A Ge concentration of the SiGe base layer is increa...	01/20/2004
6680235	Method for fabricating a selective eptaxial HBT emitter According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a top surface. The heterojunction bipolar transistor further comprises an epitaxial emitter selectively situated on the top surface of the base. For example...	01/20/2004

«First «Previous1 2 3 4 5 Next»Last»

PatentStorm

Quotables

PatentStorm News

Class 257/E29.193 - Comprising lattice mismatched active layers (e.g., SiGe strained layer transistors) (EPO)