Class 257/E29.156 - Including silicide layer contacting silicon layer (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.155. This
No. of patents: 222
Last issue date: 09/23/2008

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Number	Title	Issue Date
7427546	Transistor device and method for manufacturing the same A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located ove...	09/23/2008
7411254	Semiconductor substrate The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a cr...	08/12/2008
7332420	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semicon...	02/19/2008
7329927	Integrated circuit devices having uniform silicide junctions Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes...	02/12/2008
7327001	PMOS transistor with compressive dielectric capping layer A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. C...	02/05/2008
7307871	SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ...	12/11/2007
7294893	Titanium silicide boride gate electrode A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the ...	11/13/2007
7256123	Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr...	08/14/2007
7247915	Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr...	07/24/2007
7129548	MOSFET structure with multiple self-aligned silicide contacts A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field eff...	10/31/2006
6696346	Method of manufacturing semiconductor device It is an object of the present invention to provide a semiconductor device capable of decreasing electric resistance of a lower electrode provided therein, as well as capable of accurately responding to external signals having high frequencies inputted th...	02/24/2004
6693001	Process for producing semiconductor integrated circuit device A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity C...	02/17/2004
6667227	Trenched gate metal oxide semiconductor device and method A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region....	12/23/2003
6642621	Capacitor-type semiconductor device It is an object of the present invention to provide a semiconductor device capable of decreasing electric resistance of a lower electrode provided therein, as well as capable of accurately responding to external signals having high frequencies inputted th...	11/04/2003
6638803	Semiconductor device and method for manufacturing the same Isolation regions 12 are formed on a silicon substrate 10 to isolate NMOS and PMOS regions in which to form NMOS and PMOS transistors respectively. A silicon oxide film 14 and an amorphous silicon film 16 are formed as a gate insulating film on the silico...	10/28/2003
6635535	Dense trench MOSFET with decreased etch sensitivity to deposition and etch processing A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insul...	10/21/2003
6627951	High speed trench DMOS A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high...	09/30/2003
6620703	Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF....	09/16/2003
6605513	Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at ...	08/12/2003
6602786	One-step process for forming titanium silicide layer on polysilicon A single rapid thermal anneal (RTA) process is used to form a low resistivity titanium silicide layer atop a polysilicon gate layer for a MOSgated device. The process employs an amorphous silicon layer formed atop the polysilicon layer, followed by formin...	08/05/2003
6593633	Method and device for improved salicide resistance on polysilicon gates The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Anothe...	07/15/2003
6586809	Semiconductor device and method for fabricating the same A gate insulating film, a gate electrode, a gate-top protection film, LDD layers and nitride film sidewalls are formed on a semiconductor substrate. Source/drain regions are formed in the semiconductor substrate. After deposition of an interlayer insulati...	07/01/2003
6583059	Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device comprises the steps of: (a) forming a thermal oxide film on a surface of a silicon layer; (b) removing the thermal oxide film; and (c) forming a silicide film on the resulting surface of the silicon layer....	06/24/2003
6579783	Method for high temperature metal deposition for reducing lateral silicidation Embodiments of the present invention generally relate to processes of making an improved salicide-gate. One embodiment of a method for forming a feature on a substrate comprises forming a gate structure on a substrate; forming spacers by the sidewalls of ...	06/17/2003
6534405	Method of forming a MOSFET device featuring a dual salicide process A method for fabricating a MOSFET device using a dual salicide formation procedure has been developed. The process features a first salicide formation procedure used to create a thick metal silicide component for a composite gate structure, with the compo...	03/18/2003
6531396	Method of fabricating a nickel/platinum monsilicide film A method of fabricating a silicide layer on a silicon region of a semiconductor structure, the method comprising the steps of: providing a semiconductor structure having at least one silicon region on a surface thereof; depositing a layer comprising nicke...	03/11/2003
6528402	Dual salicidation process A dual salicidation process has the steps of: covering a sacrificial layer on the top of a polysilicon gate conductor; performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor; forming source/d...	03/04/2003
6524939	Dual salicidation process A dual salicidation process is used on a semiconductor substrate which has a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and L...	02/25/2003
6521964	Device having spacers for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a ...	02/18/2003
6521527	Semiconductor device and method of fabricating the same Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+ -type gate electrode which are formed on...	02/18/2003
6512296	Semiconductor structure having heterogenous silicide regions having titanium and molybdenum A process for forming heterogeneous silicide structures on a semiconductor substrate (10) includes implanting molybdenum ions into selective areas of the semiconductor substrate (10) to form molybdenum regions (73, 74, 75, 76). Titanium is then deposited ...	01/28/2003
6509618	Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a ...	01/21/2003
6506652	Method of recessing spacers to improved salicide resistance on polysilicon gates A method and device for improved salicide resistance in polysilicon gates under 0.20 μm. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a ...	01/14/2003
6495438	Titanium polycide gate electrode and method of forming a titanium polycide gate electrode of a semiconductor device The present invention provides a method of forming a titanium polycide gate electrode. The method comprises the step of: forming a gate insulation film a top surface of a semiconductor substrate; forming a polysilicon layer on the gate insulation film; fo...	12/17/2002
6482739	Method for decreasing the resistivity of the gate and the leaky junction of the source/drain This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in ...	11/19/2002
6479403	Method to pattern polysilicon gates with high-k material gate dielectric A method of patterning a gate electrode layer having an underlying high-k dielectric layer comprising the following sequential steps. A substrate is provided. A high-k dielectric layer is formed over the substrate. A gate electrode layer is formed over th...	11/12/2002
6468900	Dual layer nickel deposition using a cobalt barrier to reduce surface roughness at silicide/junction interface A method for manufacturing a semiconductor device employing mixed metal silicide technology is disclosed. The method comprises providing a semiconductor device having a doped silicon region, such as a source/drain, sequentially layering a first metal comp...	10/22/2002
6468904	RPO process for selective CoSix formation A method for forming an improved RPO layer by using a composite layer and a two-step etching process in a salicide process in the fabrication of integrated circuits is described. Isolation areas are formed on a semiconductor substrate surrounding and elec...	10/22/2002
6462390	Multi-film capping layer for a salicide process A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable t...	10/08/2002
6440806	Method for producing metal-semiconductor compound regions on semiconductor devices A method of making metal-semiconductor compound regions, such as silicide regions, includes forming a metal layer on a surface of a semiconductor device, performing a first annealing to form metal-semiconductor regions, and depositing additional metal wit...	08/27/2002

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Class 257/E29.156 - Including silicide layer contacting silicon layer (EPO)