Class 257/E29.154 - Silicon gate conductor material (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.15. This
No. of patents: 134
Last issue date: 01/27/2004

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Number	Title	Issue Date
6682994	Methods for transistor gate formation using gate sidewall implantation Methods are disclosed for semiconductor device fabrication in which MOS transistor gates are to be formed. Polysilicon gate structures and sidewall spacers are formed, with upper portions of the gate sidewalls exposed. Angled implantation processing is em...	01/27/2004
6682992	Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into t...	01/27/2004
6646326	Method and system for providing source/drain-gate spatial overlap engineering for low-power devices A method and system for providing a semiconductor device on a substrate are disclosed. The method and system include providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes...	11/11/2003
6627951	High speed trench DMOS A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high...	09/30/2003
6621114	MOS transistors with high-k dielectric gate insulator for reducing remote scattering The present invention relates to a MOS transistor structure and method of manufacture which provides a high-k dielectric gate insulator for reduced gate current leakage while concurrently reducing remote scattering, thereby improving transistor carrier mo...	09/16/2003
6611032	Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) fo...	08/26/2003
6566210	Method of improving gate activation by employing atomic oxygen enhanced oxidation The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall...	05/20/2003
6566209	Method to form shallow junction transistors while eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele...	05/20/2003
6559037	Process for producing semiconductor device having crystallized film formed from deposited amorphous film A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced ...	05/06/2003
6531750	Shallow junction transistors which eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele...	03/11/2003
6521527	Semiconductor device and method of fabricating the same Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+ -type gate electrode which are formed on...	02/18/2003
6492676	Semiconductor device having gate electrode in which depletion layer can be generated A semiconductor device including a first gate electrode having a first plane provided opposite to a first semiconductor region where a channel is to be formed with a first gate insulation film interposed therebetween; a second gate insulation film includi...	12/10/2002
6482725	Gate formation method for reduced poly-depletion and boron penetration Depletion of dopant from polysilicon gate layers with attendant dopant penetration of underlying gate oxide layers of silicon-based MOS and CMOS transistor devices are reduced or substantially eliminated by a process wherein a thin, high-quality silicon o...	11/19/2002
6482709	Manufacturing process of a MOS transistor A manufacturing method of a MOS transistor. A gate oxide layer and a polysilicon layer are successively formed on a substrate. A nitrogen ion implantation is performed to implant nitrogen ions into the contact region of the polysilicon layer with the gate...	11/19/2002
6475887	Method of manufacturing semiconductor device A semiconductor device which can effectively prevent impurity diffusion in heat treatment for electrically activating the impurity, and a manufacturing method thereof are disclosed. In the semiconductor device, a diffusion preventing layer having a depth ...	11/05/2002
6476462	MOS-type semiconductor device and method for making same An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semico...	11/05/2002
6455372	Nucleation for improved flash erase characteristics The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain siz...	09/24/2002
6455890	Structure of fabricating high gate performance for NROM technology A structure of fabricating high gate performance for NROM technology. The method at least includes the following steps. First of all, a tunnel oxide layer on the silicon substrate. Then, a amorphous silicon layer on the tunnel oxide layer, and a poly-SiGe...	09/24/2002
6451644	Method of providing a gate conductor with high dopant activation An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have a gate conductor with dopants distributed in a box-like distribution. The dopants also achieve high electrical activation. The MOSFETs utilize gate structures with heavily doped po...	09/17/2002
6432783	Method for doping a semiconductor device through a mask The manufacturing method produces a semiconductor in which current is not generated during the off state by reducing the electric field at the corner of an active region. The method includes patterning a gate material layer on a predetermined portion on t...	08/13/2002
6392280	Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielec...	05/21/2002
6380015	MOSFETs with improved short channel effects and method of making the same In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polys...	04/30/2002
6362038	Low and high voltage CMOS devices and process for fabricating same CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a sin...	03/26/2002
6348719	Using a change in doping of poly gate to permit placing both high voltage and low voltage transistors on the same chip A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dop...	02/19/2002
6306742	Method for forming a high dielectric constant insulator in the fabrication of an integrated circuit A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric...	10/23/2001
6300664	Semiconductor device and method of fabricating the same Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+ -type gate electrode which are formed on...	10/09/2001
6297109	Method to form shallow junction transistors while eliminating shorts due to junction spiking A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first ele...	10/02/2001
6287906	Semiconductor device having MOS transistor and method of manufacturing the same An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpend...	09/11/2001
6274915	Method of improving MOS device performance by controlling degree of depletion in the gate electrode A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to a...	08/14/2001
6252270	Increased cycle specification for floating-gate and method of manufacture thereof A programmable semiconductor device and a method of manufacturing the same. The device includes: (1) a substrate composed at least in part of silicon, (2) a dielectric layer located over the substrate and (3) a control gate located over the dielectric lay...	06/26/2001
6236088	Semiconductor device gate structure for thermal overload protection An arrangement for providing thermal overload protection for a gated electrode power semiconductor device comprises connecting the gate electrode of the device in a series circuit between the gate electrode terminal applying a bias voltage to the gate ele...	05/22/2001
6232208	Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile A semiconductor device is provided with a gate electrode having a substantially rectangular profile by depositing a layer of amorphous or microcrystalline silicon. The amorphous or microcrystalline silicon is doped with impurities, before patterning to fo...	05/15/2001
6222251	Variable threshold voltage gate electrode for higher performance mosfets A transistor is formed on the substrate (10) with a graded doping profile for the gate electrode (22). This graded profile is performed for an N-channel transistor by depositing the gate electrode with two separate layers of material. The first layer is a...	04/24/2001
6204155	Semiconductor device and production thereof A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced ...	03/20/2001
6187656	CVD-based process for manufacturing stable low-resistivity poly-metal gate electrodes A process for forming a W-poly gate stack (110) comprising the steps of: (1) deposition of doped polysilicon (112) on a thin dielectric layer (108) covered substrate (102), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx ...	02/13/2001
6165821	P channel radhard device with boron diffused P-type polysilicon gate A MOS gated device is resistant to both high radiation and SEE environments. Spaced, N-type body regions are formed in the surface of a P-type substrate of a semiconductor wafer. P-type dopants are introduced into the surface within each of the channel re...	12/26/2000
6159809	Method for manufacturing surface channel type P-channel MOS transistor while suppressing P-type impurity penetration In a method for manufacturing a surface channel type P-channel MOS transistor, a gate insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the gate insulating layer. Then, a P-type impurity diffusion preventing operat...	12/12/2000
6159783	Semiconductor device having MOS transistor and method of manufacturing the same An MOS transistor capable of improving hot carrier resistance and a method of manufacturing thereof are provided. In the MOS transistor, nitrogen is introduced in a sidewall oxide film, so that a concentration distribution of nitrogen in a section perpend...	12/12/2000
6153470	Floating gate engineering to improve tunnel oxide reliability for flash memory devices A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunn...	11/28/2000
6146953	Fabrication method for mosfet device A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the act...	11/14/2000

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Class 257/E29.154 - Silicon gate conductor material (EPO)