Class 257/E29.128 - With insulated gate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E29.127. This
No. of patents: 60
Last issue date: 08/12/2008

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Number	Title	Issue Date
7410855	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f...	08/12/2008
7405455	Semiconductor constructions and transistor gates One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer. The first layer comprises silicon and the second layer comprises a metal. The line has at least one sidewa...	07/29/2008
7391085	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f...	06/24/2008
7378713	Semiconductor devices with dual-metal gate structures and fabrication methods thereof Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped r...	05/27/2008
7332756	Damascene gate structure with a resistive device A semiconductor structure having a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. The structure includes a first dielectric layer having a first opening and a second opening formed on the semiconductor substrate, and one o...	02/19/2008
7317230	Fin FET structure A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby r...	01/08/2008
7217971	Miniaturized semiconductor device with improved dielectric properties Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as...	05/15/2007
7115959	Method of forming metal/high-k gate stacks with high mobility The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the ga...	10/03/2006
6534857	Thermally balanced power transistor A high power transistor structure comprised of a plurality of field effect transistors fabricated in parallel on a common semiconductor chip and wherein the gate electrodes of the field effect devices are in the form of parallel finger elements having a v...	03/18/2003
6327187	EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material h...	12/04/2001
6236088	Semiconductor device gate structure for thermal overload protection An arrangement for providing thermal overload protection for a gated electrode power semiconductor device comprises connecting the gate electrode of the device in a series circuit between the gate electrode terminal applying a bias voltage to the gate ele...	05/22/2001
6208557	EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material h...	03/27/2001
6124619	Semiconductor device including upper, lower and side oxidation-resistant films In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36...	09/26/2000
5892247	Semiconductor device and a manufacturing method thereof The semiconductor device comprises a substrate, a first conductive layer formed on the substrate with a first insulating layer inserted therebetween, thereby to constitute a first gate electrode, a second conductive layer selectively formed on the first g...	04/06/1999
5757044	Electrically erasable and programmable read only memory cell with split floating gate for preventing cell from over-erase A floating gate type field effect transistor has a plurality of floating gate sub-electrodes on a lower gate oxide layer electrically isolated from one another; even if one of the floating gate sub-electrodes changes a part of a channel region thereunder ...	05/26/1998
5643811	Method of making field effect transistor for high-frequency operation A field effect transistor including a gate electrode divided into a plurality of parts in the gate-length direction. The gate electrode makes Schottky-contacts with a semiconductor layer or is formed on the semiconductor layer through a gate insulating fi...	07/01/1997
5640031	Spacer flash cell process A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The c...	06/17/1997
5614747	Method for manufacturing a flash EEPROM cell The present invention discloses a split gate type flash EEPROM cell and a method of manufacturing the same which can prevent over-erasure of the flash EEPROM cell and decrease the cell area by forming a floating gate in the form of a spacer on a side wall...	03/25/1997
5612557	Semiconductor device having an inter-layer insulating film disposed between two wiring layers A semiconductor device includes a substrate, a first insulating film carried on the substrate, a first conductor layer having sides and carried on the first insulting film, and an interlayer insulating film overlying the first conductor layer and the firs...	03/18/1997
5606190	Microelectronic circuit structure having improved structural fineness and method for manufacturing same A microelectronic circuit structure has a semiconductor layer and a dielectric layer that are arranged neighboring one another. The dielectric layer comprises a charge distribution localized close to the boundary surface to the semiconductor layer which e...	02/25/1997
5597749	Method of making nonvolatile memory cell with crystallized floating gate The nonvolatile memory cell of this invention includes a floating gate formed of an ultra-thin polycrystalline silicon film. Since the memory cell includes such an ultra-thin floating gate with a smooth surface, problems occurring in the patterning for th...	01/28/1997
5569945	Stepped floating gate EPROM device Fabrication of a MOSFET comprises, forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patter...	10/29/1996
5506431	Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications A structure for low voltage, high density, non-volatile memory cell, with ability to write electrically using the CACT or Channel Accelerated Carrier Tunneling method for programming memories and erase electrically by tunneling, having separate regions fo...	04/09/1996
5493140	Nonvolatile memory cell and method of producing the same The nonvolatile memory cell of this invention includes a floating gate formed of an ultra-thin polycrystalline silicon film. Since the memory cell includes such an ultra-thin floating gate with a smooth surface, problems occurring in the patterning for th...	02/20/1996
5483487	Electrically programmable memory device with improved dual floating gates An improved method and structure for producing electrically programmable read only memory devices (EPROM's) and flash EPROM's having dual sidewall floating gates is provided. A conformal polysilicon layer is formed over a masking line with vertical sidewa...	01/09/1996
5479368	Spacer flash cell device with vertically oriented floating gate A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The c...	12/26/1995
5476801	Spacer flash cell process A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The c...	12/19/1995
5461249	Nonvolatile semiconductor memory device and manufacturing method therefor A drain diffusion layer acting as a drain of both of a memory transistor and a selection transistor, and a source diffusion layer acting as a source of both of the memory transistor and the selection transistor are formed in a semiconductor substrate. A f...	10/24/1995
5440158	Electrically programmable memory device with improved dual floating gates An improved method and structure for producing electrically programmable read only memory devices (EPROM's) and flash EPROM's having dual sidewall floating gates is provided. A conformal polysilicon layer is formed over a masking line with vertical sidewa...	08/08/1995
5414287	Process for high density split-gate memory cell for flash or EPROM A method and structure for manufacturing a high-density split gate memory cell, for a flash memory or EPROM, is described. Silicon islands are formed from a silicon substrate implanted with a first conductivity-imparting dopant. A first dielectric layer s...	05/09/1995
5402374	Non-volatile semiconductor memory device and memory circuit using the same In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film...	03/28/1995
5395779	Process of manufacture of split gate EPROM device Fabrication of a MOSFET comprises, forming a dielectric layer on a substrate and a sacrificial structure on portions of the dielectric layer, forming a first polysilicon layer over the sacrificial structure and other exposed surfaces of the device, patter...	03/07/1995
5343424	Split-gate flash EEPROM cell and array with low voltage erasure Each unit cell (10) of a flash EEPROM array (50) includes a control gate (38) having a section (38b) disposed in series between a program section (34a) of a floating gate (34) and a source (18) to provide threshold voltage control for erasure. The floatin...	08/30/1994
5306938	Lateral MOSFET A lateral MOSFET includes a back gate region, a part of its surface being a channel region. The back gate region surrounds the drain region, while being in contact with a part of the periphery of the drain region. With this configuration, when a high volt...	04/26/1994
5302846	Semiconductor device having improved vertical insulated gate type transistor A semiconductor device is provided having an insulated gate type transistor comprising a semiconductor body. First and second semiconductor regions define source and drain regions buried in the semiconductor body. A third semiconductor region defines a ch...	04/12/1994
5298442	Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry Power MOSFET apparatus, and method for its production, that suppresses voltage breakdown near the gate, using a polygon-shaped trench in which the gate is positioned, using a shaped deep body junction that partly lies below the trench bottom, and using sp...	03/29/1994
5274261	Integrated circuit degradation resistant structure A transistor (10) having a gate region formed with a thin oxide layer (28) over the gate (24). The gate (24) has a polysilicon spacer (34) formed adjacent to the gate (24) for increasing the resistance to channel hot-electron-induced degradation....	12/28/1993
5254867	Semiconductor devices having an improved gate A MOSFET comprises a silicon substrate 1 having a source/drain region 7b formed in a surface region thereof, an insulating film 3 formed of silicon oxide, and a gate electrode 4a. The side surface region of the electrode 4a is covered with an insulating f...	10/19/1993
5248893	Insulated gate field effect device with a smoothly curved depletion boundary in the vicinity of the channel-free zone An apparatus and method for forming an insulated gate field effect device including a first conductivity-type semiconductor substrate having a concave with a curved surface formed on the main surface, an insulating film formed on the major surface includi...	09/28/1993
5227655	Field effect transistor capable of easily adjusting switching speed thereof Herein disclosed is a vertical-type field effect transistor having a parallel connection of a diode and a resistor between the gate bonding pad and the gate electrode of the transistor to adjust the switching speed of the transistor without changing the o...	07/13/1993

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Class 257/E29.128 - With insulated gate (EPO)