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| Number | Title | Issue Date |
| 7238973 | Semiconductor member, manufacturing method thereof, and semiconductor device An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain induction porous layer or a porous silicon layer and strain induction porous layer. An SiGe layer and st... | 07/03/2007 |
| 6686646 | Diverse band gap energy level semiconductor device Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.... | 02/03/2004 |
| 6674099 | MISFET A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drai... | 01/06/2004 |
| 6657278 | Diverse band gap energy level semiconductor device Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.... | 12/02/2003 |
| 6645831 | Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide A wafer pair comprising a substantially defect-free germanium wafer and methods of making the same. The wafer pair comprises the substantially defect-free germanium wafer directly bonded to a silicon wafer. The method of making the wafer pair comprises pl... | 11/11/2003 |
| 6645836 | Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly ha... | 11/11/2003 |
| 6621131 | Semiconductor transistor having a stressed channel A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and... | 09/16/2003 |
| 6597016 | Semiconductor device and method for fabricating the same An Si1-y Gey layer (where 0 | 07/22/2003 |
| 6576532 | Semiconductor device and method therefor A heteroepitaxial structure is made using nanocrystals that are formed closer together than normal lithography patterning would allow. The nanocrystals are oxidized and thus selectively etchable with respect to the substrate and surrounding material. In o... | 06/10/2003 |
| 6518197 | Method for manufacturing semiconductor device According to a method for manufacturing a semiconductor device having a junction boundary where SiGe of a first conductivity type and Si or SiGe of a second conductivity type come in contact with each other, a portion where the junction boundary is expose... | 02/11/2003 |
| 6475869 | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material cont... | 11/05/2002 |
| 6403976 | Semiconductor crystal, fabrication method thereof, and semiconductor device A Si1-x Gex /Si1-y Cy short-period superlattice which functions as a single SiGeC layer is formed by alternately growing Si1-x Gex layers (0 | 06/11/2002 |
| 6274894 | Low-bandgap source and drain formation for short-channel MOS transistors A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides wit... | 08/14/2001 |
| 6239463 | Low resistance power MOSFET or other device containing silicon-germanium layer A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the... | 05/29/2001 |
| 6207977 | Vertical MISFET devices The present invention relates to processes for fabrication of Vertical MISFET devices or a stack of several of such devices. The Vertical MISFET device comprises a highly doped drain region, a non or lowly doped channel region and a source region forming ... | 03/27/2001 |
| 6198141 | Insulated gate semiconductor device and method of manufacturing the same Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impur... | 03/06/2001 |
| 6187641 | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first materia... | 02/13/2001 |
| 6124627 | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first materia... | 09/26/2000 |
| 6004137 | Method of making graded channel effect transistor A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transcon... | 12/21/1999 |
| 5963800 | CMOS integration process having vertical channel The present invention relates to processes for fabrictation of Vertical MISFET devices or a stack of several Vertical MISFET devices having high fabrication yield.... | 10/05/1999 |
| 5923070 | Semiconductor device having an element inclusion region for reducing stress caused by lattice mismatch A semiconductor device improves its electrical characteristics by reducing crystal defects in the vicinity of junction interfaces between a semiconductor layer, and a metal compound layer composed of semiconductor and metal elements, and between an epitax... | 07/13/1999 |
| 5920088 | Vertical MISFET devices The present invention relates to Silicon Germanium-based Vertical MISFET devices allowing smaller device size and exhibiting significant advantages over prior devices related to the reduction of drain induced barrier lowering and parasitic capacitance and... | 07/06/1999 |
| 5914504 | DRAM applications using vertical MISFET devices The present invention relates to RAM circuits comprising memory cells and logic circuitry wherein each of the memory cells comprise at least one Vertical MISFET device comprising a stack of several layers a source layer, a channel layer, a drain layer and... | 06/22/1999 |
| 5821577 | Graded channel field effect transistor A MISFET having a graded semiconductor alloy channel layer of silicon germanium in which the germanium is graded to a single peak percentage level. The single peak percentage level defines the location of the charge carriers within the layer. The transcon... | 10/13/1998 |
| 5734183 | Heterojunction bipolar transistor structure A semiconductor device is provided with an emitter area and a collector area of a first conductive type and a base area of a second conductive type, arranged in a horizontal structure. The semiconductor device comprises an area constituting at least a par... | 03/31/1998 |
| 5686734 | Thin film semiconductor device and photoelectric conversion device using the thin film semiconductor device A high performance thin film semiconductor device having a heterojunction such as a photoelectric conversion device is disclosed. In accordance with the present invention, the thin film semiconductor device comprises a thin semiconductor layer which forms... | 11/11/1997 |
| 5685946 | Method of producing buried porous silicon-geramanium layers in monocrystalline silicon lattices Lattices of alternating layers of monocrystalline silicon and porous silicon-germanium have been produced. These single crystal lattices have been fabricated by epitaxial growth of Si and Si--Ge layers followed by patterning into mesa structures. The mesa... | 11/11/1997 |
| 5640043 | High voltage silicon diode with optimum placement of silicon-germanium layers A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa p... | 06/17/1997 |
| 5632812 | Diamond electronic device and process for producing the same A diamond electronic device constituted of a diamond crystal formed on a substrate comprises a diamond crystal having the ratio (h/L) of length (h) of the diamond crystal in direction substantially perpendicular to the face of the substrate to length (L) ... | 05/27/1997 |
| 5473171 | High-dielectric constant oxides on semiconductors using a Ge buffer layer This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelec... | 12/05/1995 |
| 5441901 | Method for forming a carbon doped silicon semiconductor device having a narrowed bandgap characteristic A IV-IV semiconductor device having a narrowed bandgap characteristic compared to silicon and method is provided. By incorporating carbon into silicon at a substitutional concentration of between 0.5% and 1.1%, a semiconductor device having a narrowed ban... | 08/15/1995 |
| 5395774 | Methods for forming a transistor having an emitter with enhanced efficiency Methods of forming a carbon containing, minority carrier barrier layer on the surface of a semiconductor, which methods may be used to form barriers between the emitter of a single crystal transistor and a polysilicon layer in electrical contact therewith... | 03/07/1995 |
| 5360986 | Carbon doped silicon semiconductor device having a narrowed bandgap characteristic and method A IV--IV semiconductor device having a narrowed bandgap characteristic compared to silicon and method is provided. By incorporating carbon into silicon at a substitutional concentration of between 0.5% and 1.1%, a semiconductor device having a narrowed ba... | 11/01/1994 |
| 5342805 | Method of growing a semiconductor material by epilaxy This invention concerns itself with an improved method of producing sharply defined misfit dislocations; (MD) with a new, inexpensive method of doping these misfit dislocations with Au; with invention that a combination of Au and Pt doping in misfit dislo... | 08/30/1994 |
| 5338942 | Semiconductor projections having layers with different lattice constants A semiconductor device comprising a semiconductor crystalline substrate having projections each thereof having an area of 0.01 μm2 to 4 μm2 or stripe projections each thereof having a width of 0.01 μm to 1 μm and semiconductor cr... | 08/16/1994 |
| 5329257 | SiGe transferred electron device and oscillator using same This invention is a three layer Six Ge1-x structure formed on a silicon substrate in which a thin, lightly doped Six Ge1-x layer is formed between two heavily doped Six Ge1-x layers. The in... | 07/12/1994 |
| 5326721 | Method of fabricating high-dielectric constant oxides on semiconductors using a GE buffer layer This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a germanium layer 28 directly or indirectly on a semiconductor substrate 20; and depositing a high-dielectric constant oxide 32 (e.g. a ferroelec... | 07/05/1994 |
| 5272365 | Silicon transistor device with silicon-germanium electron gas hetero structure channel A metal oxide semiconductor field effect transistor with heterostructure has a silicon substrate. Heavily-doped source and drain layers which are different in conductivity type from the substrate are spaced apart from each other in the surface portion of ... | 12/21/1993 |
| 5256888 | Transistor device apparatus employing free-space electron emission from a diamond material surface An electron device (100, 110, 200, 300, 400, 500) comprised of a semiconductor transistor such as a bipolar or field effect transistor, a diamond material layer (107, 206, 305), and a distally disposed anode is provided.... | 10/26/1993 |
| 5241197 | Transistor provided with strained germanium layer A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose ... | 08/31/1993 |
