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| Number | Title | Issue Date |
| 7436069 | Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A ... | 10/14/2008 |
| 7432551 | SOI semiconductor device including a guard ring region An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor dev... | 10/07/2008 |
| 7432173 | Methods of fabricating silicon-on-insulator substrates having a laser-formed single crystalline film In some methods of fabricating a silicon-on-insulator substrate, a semiconductor substrate is provided that includes a single crystalline structure within at least a defined region thereof. A first insulating film is formed on the defined region of the semiconductor... | 10/07/2008 |
| 7423323 | Semiconductor device with raised segment A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material ... | 09/09/2008 |
| 7423313 | NAND-type semiconductor storage device and method for manufacturing same According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate ... | 09/09/2008 |
| 7420249 | Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insula... | 09/02/2008 |
| 7420248 | Programmable random logic arrays using PN isolation Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type,... | 09/02/2008 |
| 7411295 | Circuit board, device mounting structure, device mounting method, and electronic apparatus A circuit board has a metal pattern that is formed on a surface of the circuit board to be connected with bumps in two-dimensional arrangement for mounting an electronic device that has the bumps. A plurality of the bumps which has even electrical potentials is elec... | 08/12/2008 |
| 7407826 | Vacuum packaged single crystal silicon device A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anch... | 08/05/2008 |
| 7405982 | Methods to improve the operation of SOI devices According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse t... | 07/29/2008 |
| 7402865 | Semiconductor device including a contact connected to the body and method of manufacturing the same A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P+ region with a high impurity concentration thereat. The surface of a body contact is provide with a... | 07/22/2008 |
| 7397081 | Sidewall semiconductor transistors A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched betwee... | 07/08/2008 |
| 7397087 | FEOL/MEOL metal resistor for high end CMOS A FEOL/MEOL metal resistor that has tight sheet resistance tolerance (on the order of about 5% or less), high current density (on the order of about 0.5 mA/micron or greater), lower parasitics than diffused resistors and lower TCR than standard BEOL metal resistors ... | 07/08/2008 |
| 7394129 | SOI wafer and method for producing it An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski s... | 07/01/2008 |
| 7391095 | Semiconductor device In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in co... | 06/24/2008 |
| 7378357 | Multiple dielectric FinFET structure and method Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on oppos... | 05/27/2008 |
| 7375397 | Semiconductor device having an SOI structure and method for manufacturing the same There is provided a semiconductor device in which the characteristic variations of a transistor and the degradation of a gate oxide layer are reduced during a WP process and a method for manufacturing the same. The semiconductor device includes a semiconductor chip ... | 05/20/2008 |
| 7372107 | SOI chip with recess-resistant buried insulator and method of manufacturing the same A semiconductor-on-insulator structure includes a substrate and a buried insulator stack overlying the substrate. The buried insulator stack includes a first dielectric layer and a recess-resistant layer overlying the first dielectric layer. A second dielectric laye... | 05/13/2008 |
| 7368341 | Semiconductor circuit arrangement with trench isolation and fabrication method An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insula... | 05/06/2008 |
| 7365396 | SOI SRAM products with reduced floating body effect A memory device is formed on a semiconductor-on-insulator (SOI) structure, the SOI structure including a substrate, an insulating layer on the substrate, and a semiconductor film on the insulating layer. The memory device includes a memory array in a memory region o... | 04/29/2008 |
| 7358571 | Isolation spacer for thin SOI devices A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor ... | 04/15/2008 |
| 7355249 | Silicon-on-insulator based radiation detection device and method Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the bu... | 04/08/2008 |
| 7352060 | Multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring substrate A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler i... | 04/01/2008 |
| 7352049 | Semiconductor device and method of manufacturing the same Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, resp... | 04/01/2008 |
| 7348609 | Thin film transistor and method of forming thin film transistor The thin film transistor has a non-transparent structure besides and insulated with the gate. Hence, the light transmitted from the substrate is blocked and the light current induced in the thin film transistor is negligible. The method uses a mask with a slit patte... | 03/25/2008 |
| 7348632 | NMOS device formed on SOI substrate and method of fabricating the same Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular... | 03/25/2008 |
| 7335952 | Semiconductor device and manufacturing method therefor To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method fo... | 02/26/2008 |
| 7329923 | High-performance CMOS devices on hybrid crystal oriented substrates An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is... | 02/12/2008 |
| 7329924 | Integrated circuits and methods of forming a field effect transistor Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semicondu... | 02/12/2008 |
| 7319252 | Methods for forming semiconductor wires and resulting devices Methods for forming a wire from silicon or other semiconductor material are disclosed. Also disclosed are various devices including such a semiconductor wire. According to one embodiment, a wire is spaced apart from an underlying substrate, and the wire extends betw... | 01/15/2008 |
| 7317226 | Patterned SOI by oxygen implantation and annealing Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein... | 01/08/2008 |
| 7314783 | Method of fabricating contact line of liquid crystal display device A contact line structure for a liquid crystal display device includes a metal line on an array substrate, a silicide layer on the metal line, an insulating layer having a contact hole exposing a first portion of the silicide layer, and a transparent conducting termi... | 01/01/2008 |
| 7312502 | Multiple dielectric FinFET structure and method Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on oppos... | 12/25/2007 |
| 7297978 | Semiconductor thin film and semiconductor device After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} o... | 11/20/2007 |
| 7297981 | Electro-optical device having a light-shielding film comprising alternating layers of silicide and nitrided silicide A light-shielding film formed above a substrate has a multilayered thin film structure, in which a thin film not containing nitrogen and a thin film containing nitrogen are alternately arranged. Since the thin film containing nitrogen is formed in the light-shieldin... | 11/20/2007 |
| 7298009 | Semiconductor method and device with mixed orientation substrate A semiconductor device includes a semiconductor body having semiconductor material of a first crystal orientation. A first transistor is formed in the semiconductor material of the first crystal orientation. An insulating layer overlies portions of the semiconductor... | 11/20/2007 |
| 7274070 | Complementary thin film transistor circuit, electro-optical device, and electronic apparatus To provide a highly reliable complementary thin film transistor circuit in which deviations in characteristics of a first-conductivity-type thin film transistor and a second-conductivity-type thin film transistor can be reduced or prevented and operated stably. A fi... | 09/25/2007 |
| 7265017 | Method for manufacturing partial SOI substrates There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region an... | 09/04/2007 |
| 7265419 | Semiconductor memory device with cell transistors having electrically floating channel bodies to store data A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with cell transistors disposed in such a manner that each of source and dr... | 09/04/2007 |
| 7262486 | SOI substrate and method for manufacturing the same The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device ... | 08/28/2007 |
