Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Number | Title | Issue Date |
| 7385223 | Flat panel display with thin film transistor A flat panel display is provided. The flat panel display includes a light emitting device and two or more thin film transistors (TFTs) having semiconductor active layers having channel regions, where the thickness of the channel regions of the TFTs are different fro... | 06/10/2008 |
| 7365377 | Semiconductor integrated circuit device using four-terminal transistors In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed i... | 04/29/2008 |
| 7348610 | Multiple layer and crystal plane orientation semiconductor substrate A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline... | 03/25/2008 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7148511 | Active matrix substrate, electro-optical device, electronic device, and method for manufacturing an active matrix substrate An active matrix substrate includes a load circuit including a first active element performing a switching operation of a load, the first active element including a semiconductor film of a substantially polycrystalline state; a drive circuit including a second activ... | 12/12/2006 |
| 7138698 | Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and... | 11/21/2006 |
| 7030551 | Area sensor and display apparatus provided with an area sensor An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon ... | 04/18/2006 |
| 6433983 | High performance output buffer with ESD protection An output buffer with built-in ESD protection is disclosed. The built-in ESD protection is preferably formed using transistors from the sea-of-transistors or sea-of-gates region of the integrated circuit, which may eliminate the need for dedicated ESD dev... | 08/13/2002 |
| 6313665 | Semiconductor integrated circuit The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends,... | 11/06/2001 |
| 6310402 | Semiconductor die having input/output cells and contact pads in the periphery of a substrate The width of an input/output forming region is matched with the minimum width adoptable as a layout interval between pads in advance. Pads corresponding to (least common multiple).div.(layout interval between pads) in number are disposed so as to correspo... | 10/30/2001 |
| 6222213 | Semiconductor integrated circuit device In order that an internal logic circuit area and an outside input/output cell group are easily connected, a plurality of input/output cell groups for performing signal transfer with an external device are each arranged in a square loop so that the interna... | 04/24/2001 |
| 6207980 | Layout method of a semiconductor device A semiconductor device includes multi-pin I/O buffers. The I/O buffers are located near an I/O pad area of the device. The multi-pin I/O buffers include multiple, generally L-shaped terminals that are connected to pads in the I/O pad area with wirings. Th... | 03/27/2001 |
| 5962899 | Electrostatic discharge protection circuit A semiconductor memory device conserves chip area by jointly connecting transistors which are respectively connected to pads adjacent to each other. The device includes first and second electrostatic discharge protection MOSFET transistors which have drai... | 10/05/1999 |
| 5914516 | Buffer circuit with wide gate input transistor In a semiconductor integrated circuit including an input-stage input buffer circuit, an input terminal of the input buffer circuit is connected to a gate of an input MOS transistor which has a gate length longer than a gate length specified in the applied... | 06/22/1999 |
| 5859448 | Alternative silicon chip geometries for integrated circuits A method for providing a triangularly shaped I/O region on the periphery of an integrated circuit in order to reduce the amount of unused surface area on the integrated circuit is disclosed. A core region within the triangularly shaped I/O region may be e... | 01/12/1999 |
| 5796299 | Integrated circuit array including I/O cells and power supply cells There is provided a semiconductor integrated circuit having peripheral cell array including I/O cells and power supply cells, the cell array comprising first type cells having second level wiring layers consisting of a reference power supply (GND) wiring ... | 08/18/1998 |
| 5777510 | High voltage tolerable pull-up driver and method for operating same A pull-up output driver circuit includes a field effect transistor (FET) fabricated in a well region having a first conductivity type. The well region, in turn, is surrounded by a semiconductor region having a second conductivity type. The FET has a sourc... | 07/07/1998 |
| 5773854 | Method of fabricating a linearly continuous integrated circuit gate array A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with... | 06/30/1998 |
| 5773856 | Structure for connecting to integrated circuitry A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one o... | 06/30/1998 |
| 5760428 | Variable width low profile gate array input/output architecture A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necess... | 06/02/1998 |
| 5751179 | Output driver for PCI bus An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and ... | 05/12/1998 |
| 5714796 | Integrated circuit device fabricated on semiconductor substrate blocking power supply lines from noise An output driver is implemented by a complementary inverter circuit responsive to an output data signal for selectively charging and discharging an external capacitive load, and the complementary inverter circuit has a p-channel enhancement type field eff... | 02/03/1998 |
| 5698903 | Bond pad option for integrated circuits An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads.... | 12/16/1997 |
| 5694078 | Semiconductor integrated circuit having regularly arranged transistor basic cells A semiconductor integrated circuit includes a chip having an element forming surface with a side thereof extending along a first direction, an output buffer portion provided on the element forming surface of the chip, a plurality of output transistors hav... | 12/02/1997 |
| 5659189 | Layout configuration for an integrated circuit gate array A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with... | 08/19/1997 |
| 5656970 | Method and structure for selectively coupling a resistive element, a bulk potential control circuit and a gate control circuit to an output driver circuit An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for contr... | 08/12/1997 |
| 5650348 | Method of making an integrated circuit chip having an array of logic gates A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with... | 07/22/1997 |
| 5619048 | Semiconductor integrated circuit device In order to lay out a driver circuit having high drivability without increasing a semiconductor chip area, a macro cell (22) such as a clock driver having a large fan-out is arranged under a feeder line (20). It is possible to feed the macro cell (22) fro... | 04/08/1997 |
| 5618740 | Method of making CMOS output buffer with enhanced ESD resistance The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output trans... | 04/08/1997 |
| 5565386 | Method of connecting to integrated circuitry A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one o... | 10/15/1996 |
| 5563438 | Rugged CMOS output stage design A rugged MOS output stage transistor having a third region formed adjacent to the drain region on the side opposite the source. The third region is doped to have a polarity opposite the drain and forms in combination with the drain an output protect diode... | 10/08/1996 |
| 5552618 | Multi-voltage-lever master-slice integrated circuit A master-slice semiconductor integrated circuit device includes a substrate for an input/output circuit section, which is segmented into a plurality of segments during a master processing step. In a slice processing step, slice cells are formed, using dif... | 09/03/1996 |
| 5552333 | Method for designing low profile variable width input/output cells An apparatus and method of (input/output) I/O design, utilizing a predetermined relationship, whereby the outer ring area of an integrated circuit die are set aside for the I/O circuits which are contained in I/O cells. The height of the I/O cell is first... | 09/03/1996 |
| 5547887 | Method of making a CMOS output pad driver with variable drive currents, ESD protection and improved leakage current behavior A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to pr... | 08/20/1996 |
| 5546033 | Output driver circuits with enhanced supply-line bounce control and improved VOH characteristic An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising... | 08/13/1996 |
| 5543651 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a semiconductor chip having a long side and a short side. The semiconductor chip includes a memory cell area occupying approximately 80 percent of the area of the semiconductor chip and an input and outpu... | 08/06/1996 |
| 5541548 | Analog output driver for gate arrays The invention concerns an analog amplifier constructed using digital transistors. The digital transistors are those contained in a gate array, and which are used for fabrication of digital devices. The analog amplifier includes an invertor, which contains... | 07/30/1996 |
| 5539223 | Wiring structure of source line used in semicustom integrated circuit A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the ... | 07/23/1996 |
| 5532509 | Semiconductor inverter layout having improved electromigration characteristics in the output node A particular layout (38) of transistors along a continuous conductor line (54), such as the transistors in a CMOS inverter, has been found which reduces breaks or voids in the conductor line due to electromigration of the conductor atoms from predominantl... | 07/02/1996 |
| 5519355 | High speed boundary scan multiplexer An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplex... | 05/21/1996 |
