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| Number | Title | Issue Date |
| 7439120 | Method for fabricating stress enhanced MOS circuits A stress enhanced MOS circuit and methods for its fabrication are provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electro... | 10/21/2008 |
| 7436029 | High performance CMOS device structures and method of manufacture A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width... | 10/14/2008 |
| 7411227 | CMOS silicide metal gate integration The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present inve... | 08/12/2008 |
| 7410817 | Liquid crystal display device including driving circuit and method of fabricating the same A method of fabricating an array substrate structure for a liquid crystal display device includes defining a display area and a non-display area on a substrate, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having a... | 08/12/2008 |
| 7408210 | Solid state image pickup device and camera An object of the present invention is to simultaneously realize the enlargement of a dynamic range and the downsizing of a pixel. An additional capacitor CS is composed by using: a first capacitor formed of a first diffusion layer, a second diffusion layer and a P w... | 08/05/2008 |
| 7405436 | Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device locate... | 07/29/2008 |
| 7402478 | Method of fabricating dual gate electrode of CMOS semiconductor device In an embodiment, a method of fabricating a dual gate electrode includes forming an initial semiconductor layer doped with impurities of a first conductivity type on a semiconductor substrate having a first region and a second region. The initial semiconductor layer... | 07/22/2008 |
| 7402847 | Programmable logic circuit and method of using same A programmable logic circuit, including programmable memory element, suitable for microprocessor applications, and a method of using the circuit are disclosed. The programmable circuit includes at least one logic cell, columns and rows of wires coupled to the logic ... | 07/22/2008 |
| 7381602 | Method of forming a field effect transistor comprising a stressed channel region A semiconductor structure comprises a transistor element formed in a substrate. A stressed layer is formed over the transistor element. The stressed layer has a predetermined tensile intrinsic stress of about 900 MPa or more. Due to this high intrinsic stress, the s... | 06/03/2008 |
| 7371628 | Method for fabricating semiconductor device A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second... | 05/13/2008 |
| 7365376 | Semiconductor integrated circuit A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power s... | 04/29/2008 |
| 7365377 | Semiconductor integrated circuit device using four-terminal transistors In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed i... | 04/29/2008 |
| 7355217 | MOS transistor structure with easy access to all nodes A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device is provided. The transistor is created with a four-metal CMOS process. A bulk connection can be made with Metal 1, which is all aro... | 04/08/2008 |
| 7345329 | Method for reduced N+ diffusion in strained Si on SiGe substrate The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N typ... | 03/18/2008 |
| 7332433 | Methods of modulating the work functions of film layers Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where t... | 02/19/2008 |
| 7332742 | Display device and electronic apparatus The invention provides a display device in which occurrence of a display defect called a ghost is prevented, and a driving method thereof, and a television set. According to the invention, a gate control signal (GWE) which has been one signal is divided into a first... | 02/19/2008 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7279746 | High performance CMOS device structures and method of manufacture A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width... | 10/09/2007 |
| 7244995 | Scrambling method to reduce wordline coupling noise A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a ... | 07/17/2007 |
| 7226851 | Method for manufacturing semiconductor device and non-volatile memory A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed... | 06/05/2007 |
| 7211840 | Transistor A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 san... | 05/01/2007 |
| 7208363 | Fabrication of local interconnect lines A method of fabricating local interconnect lines (LILs) of a CMOS structures, the method comprising etching an inter layer dielectric (ILD) material of the CMOS structure at a first temperature to form one or more holes and one or more slits; and etching an etch-sto... | 04/24/2007 |
| 7183599 | CMOS image sensor having test pattern therein and method for manufacturing the same The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively. The method includes steps of: forming an FOX area on a semiconductor substrate so as to define an act... | 02/27/2007 |
| 7183594 | Configurable gate array cell with extended poly gate terminal A configurable gate array cell contains at least two doping zones of a different conduction type and a poly gate terminal. In a plan view representation of the gate array cell, the poly gate terminal, with at least one section, extends further than the doping zones ... | 02/27/2007 |
| 7176090 | Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider... | 02/13/2007 |
| 7119383 | Arrangement of wiring lines including power source lines and channel wirings of a semiconductor integrated circuit having plural cells A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source l... | 10/10/2006 |
| 6784472 | Semiconductor device and method for fabricating the same A semiconductor device comprises a first transistor 38a having a first gate electrode 22; a second transistor 38b having a second gate electrode 34 which is different from the first gate electrode; an insulation film 28 | 08/31/2004 |
| 6693315 | Semiconductor device with an active region and plural dummy regions There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns c... | 02/17/2004 |
| 6690056 | EEPROM cell on SOI A non-volatile storage cell manufactured in a standard CMOS process in silicon on insulator is described. The cell is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator starting substrates. Two versions of the... | 02/10/2004 |
| 6690073 | Semiconductor integrated circuit making use of standard cells A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by ... | 02/10/2004 |
| 6684378 | Method for designing power supply circuit and semiconductor chip A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor sect... | 01/27/2004 |
| 6675361 | Method of constructing an integrated circuit comprising an embedded macro The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant ... | 01/06/2004 |
| 6670262 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed. A silicon oxide film, a polysilicon film and a silicon oxide film are formed in the order named on a silicon substrate. Then, the ... | 12/30/2003 |
| 6667506 | Variable capacitor with programmability Multiple variations of a variable capacitor or varactor 10 with built-in programmability; exhibiting high quality, Q, factors; manufactured in a standard CMOS process in silicon on insulator. The cell 10 is manufactured in a standard single polysilicon la... | 12/23/2003 |
| 6656803 | Radiation hardened semiconductor memory A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure incl... | 12/02/2003 |
| 6650143 | Field programmable gate array based upon transistor gate oxide breakdown A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and a second terminal, the first terminal connected to a colum... | 11/18/2003 |
| 6643835 | Computer-aided design supporting system in which cells can be arranged independently A computer-aided design supporting system for a semiconductor device includes a cell library, an arranging tool and a wiring tool. The cell library stores a plurality of logic cell patterns, a plurality of power supply cell patterns, and a plurality of gr... | 11/04/2003 |
| 6635935 | Semiconductor device cell having regularly sized and arranged features In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the... | 10/21/2003 |
| 6621325 | Structures and methods for selectively applying a well bias to portions of a programmable device Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integr... | 09/16/2003 |
| 6617620 | Gate array with border element A gate array comprises a core cell having a plurality of logic gates, a power supply pattern provided beside the core cell for providing electrical power to the core cell, and a border element provided beside the power supply pattern for providing capacit... | 09/09/2003 |
