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A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7122869 | Nonvolatile semiconductor memory device in which selection transistors and memory transistors have different impurity concentration distributions A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, an... | 10/17/2006 |
| 6700821 | Programmable mosfet technology and programmable address decode and correction Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circu... | 03/02/2004 |
| 6696712 | Semicustom IC having adjacent macrocells A semicustom IC including a plurality of basic cells disposed on a semiconductor substrate, a first macrocell, a second macrocell adjacent to the first macrocell, and a power supply line. The first macrocell and the second macrocell are each formed using ... | 02/24/2004 |
| 6683335 | Gate array layout for interconnect In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate o... | 01/27/2004 |
| 6525962 | High current and/or high speed electrically erasable memory cell for programmable logic devices An electrically erasable programmable logic device (EEPLD) cell (100) is disclosed. A folded floating gate (110) and folded select gate (108) can form two parallel read current paths (Isense0 and Isense1). A first read current path (Isense0) may be formed... | 02/25/2003 |
| 6515510 | Programmable logic array with vertical transistors A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and ... | 02/04/2003 |
| 6504186 | Semiconductor device having a library of standard cells and method of designing the same In a semiconductor device provided with a plurality of standard cells each comprising an input terminal and MOS transistors, a diffused region having a substantially negligibly small resistance is formed in a semiconductor substrate, and the input termina... | 01/07/2003 |
| 6486703 | Programmable logic array with vertical transistors A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and ... | 11/26/2002 |
| 6445214 | Semiconductor integrated circuit The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends,... | 09/03/2002 |
| 6399400 | Methods and apparatuses for binning partially completed integrated circuits based upon test results A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. Performance and/or elect... | 06/04/2002 |
| 6307248 | Definition of anti-fuse cell for programmable gate array application A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is ... | 10/23/2001 |
| 6308309 | Place-holding library elements for defining routing paths Described is a method of using place-holding cells, or "stopper cells," to force a place-and-route tool to route a selected signal path through a particular physical location on a semiconductor die. In one method, phantom blocks, created from the design s... | 10/23/2001 |
| 6271548 | Master slice LSI and layout method for the same A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-u... | 08/07/2001 |
| 6208165 | Semiconductor integrated circuit In a semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of the standard cells has a first side and a second side ... | 03/27/2001 |
| 6208164 | Programmable logic array with vertical transistors A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and ... | 03/27/2001 |
| 6194252 | Semiconductor device and manufacturing method for the same, basic cell library and manufacturing method for the same, and mask There are provided a semiconductor device, basic cell library, a method for manufacturing a semiconductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effe... | 02/27/2001 |
| 6180998 | DRAM with built-in noise protection A dynamic random access memory (DRAM) segment incorporates at least one shielding conductor spaced from a matrix of memory cells above the substrate and a well formed in the substrate which contains the memory cells. The shielding conductor primarily shie... | 01/30/2001 |
| 6137728 | Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the co... | 10/24/2000 |
| 6133582 | Methods and apparatuses for binning partially completed integrated circuits based upon test results A gate array integrated circuit wafer is formed having M-N generic metal interconnection layers and having performance and/or electrical testing circuits which are operative using only the M-N generic metal interconnection layers. The performance and elec... | 10/17/2000 |
| 6107874 | Semiconductor integrated circuit device produced from master slice and having operation mode easily changeable after selection on master slice A semiconductor integrated circuit device is responsive to a potential level applied to a signal pad connected to a mode changer, and the mode changer causes a mode selector to change a control signal between a first level indicative of a certain combinat... | 08/22/2000 |
| 6084256 | Semiconductor integrated circuit device A semiconductor integrated circuit has a dummy gate electrode layer formed on a semiconductor substrate, with a gate insulation film interposed. On the first layer insulation film formed on the top of the dummy gate electrode layer, the first signal line ... | 07/04/2000 |
| 6060784 | Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions An interconnection layer extends across at least a macro cell region and at least a circuit region other than the macro cell region, the macro cell region and the circuit region being monolithically integrated into a semiconductor device, wherein the inte... | 05/09/2000 |
| 6046477 | Dense SOI programmable logic array structure A semiconductor device array having silicon device islands isolated from the substrate by an insulator. High array density is achieved by forming source and drain interconnects in the space between the islands. Also disclosed are processes for forming and... | 04/04/2000 |
| 6002155 | Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnecti... | 12/14/1999 |
| 5977810 | Clock driver circuit and semiconductor integrated circuit device A clock driver circuit includes a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common li... | 11/02/1999 |
| 5945846 | Clock driver circuit in a centrally located macro cell layout region A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a ... | 08/31/1999 |
| 5937281 | Method to form metal-to-metal antifuse for field programmable gate array applications using liquid phase deposition (LPD) A method of fabricating an antifuse structure for field programmable gate array (FPGA) applications is described. First, a field oxide layer for isolation is grown on the semiconductor silicon substrate. Then, a bottom electrode, a thin dielectric layer a... | 08/10/1999 |
| 5936285 | Gate array layout to accommodate multi-angle ion implantation A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/out... | 08/10/1999 |
| 5923075 | Definition of anti-fuse cell for programmable gate array application A method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is described. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is ... | 07/13/1999 |
| 5914625 | Clock driver circuit and semiconductor integrated circuit device A clock driver circuit comprises a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common l... | 06/22/1999 |
| 5910725 | Integrated circuit output power supply transient voltage protection circuit A circuit for limiting voltage transient excursions on a power supply node is disclosed. The circuit includes a first field effect transistor dispose to provide a capacitance and having source and drain electrodes coupled to said external supply node path... | 06/08/1999 |
| 5872027 | Master slice type integrated circuit system having block areas optimized based on function A master slice type gate array has a plurality of block areas. Each block area includes a plurality of basic cells arranged in a matrix. Different block areas have transistors with different channel widths. Within each of the block areas, a plurality of b... | 02/16/1999 |
| 5847421 | Logic cell having efficient optical proximity effect correction There are provided a semiconductor device, basic cell library, a method for manufacturing a semiconductor device, and a method and mask for forming a basic cell library which can reduce the amount of poly-data to be corrected by the optical proximity effe... | 12/08/1998 |
| 5796129 | Master slice type integrated circuit system having block areas optimized based on function A master slice type gate array has a plurality of block areas. Each block area includes a plurality of basic cells arranged in a matrix. Different block areas have transistors with different channel widths. Within each of the block areas, a plurality of b... | 08/18/1998 |
| 5793068 | Compact gate array The gate array (10) has a first doped region (14) in a semiconductor substrate (12) and a plurality of contacts (20-20"', 21-21") arranged in rows and columns to the first doped region (14) organized with contacts of each row offset in a column (25) that ... | 08/11/1998 |
| 5701021 | Cell architecture for mixed signal applications A cell architecture for mixed signal applications is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a transistor arrangement in which substrate taps are located adjacent to the transistor pairs. This pro... | 12/23/1997 |
| 5698872 | Semiconductor memory wherein metallic interconnection layer is applied with the same potential as word line and is connected to word line in regions other than memory cells Memory cells, which serve as basic cells, are arranged in a matrix pattern. The memory cells are each provided with a word line which is integral with the gate electrode of a switch element and which is formed of polysilicon. A metallic interconnection la... | 12/16/1997 |
| 5656850 | Microelectronic integrated circuit including hexagonal semiconductor "and" g A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first... | 08/12/1997 |
| 5631581 | Microelectronic integrated circuit including triangular semiconductor "and" gate device A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery. First ... | 05/20/1997 |
