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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 6198117 | Transistor having main cell and sub-cells A transistor formed in a master slice manner is disclosed for use in radio frequency range, the transistor includes a main transistor cell operating as a smallest transistor in scale among a product group of transistors, and sub-transistor cells are arran... | 03/06/2001 |
| 5517040 | Personalizable semiconductor chips for analog and analog/digital circuits A computer converts a description of an analog circuit to a physical representation in terms of devices on a personalizable chip. The devices are placed and wired automatically for fabrication of the chip. Descriptions of resistors in the circuit are expa... | 05/14/1996 |
| 5455191 | Method of fabricating an ASIC cell having multiple contacts A high density ASIC cell provides customization solely at the polysilicon #2, insulator #3 levels. High density is achieved by permitting a metal #1 trace to traverse an underlying transistor, without requiring space between adjacent transistors to facili... | 10/03/1995 |
| 5440153 | Array architecture with enhanced routing for linear asics A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capa... | 08/08/1995 |
| 5244832 | Method for fabricating a poly emitter logic array and apparatus produced thereby A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a bu... | 09/14/1993 |
| 5124776 | Bipolar integrated circuit having a unit block structure A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first dire... | 06/23/1992 |
| 5101258 | Semiconductor integrated circuit device of master slice approach In a semiconductor integrated circuit device of master slice approach according to this invention, regions on basic elements which are not used and isolation areas serve as wiring regions. Resistive elements are formed on the regions on the basic elements... | 03/31/1992 |
| 5068702 | Programmable transistor An improved cell structure and method for making the same for semicustom chips which can be connected at the metalization step to form either an NPN or a PNP transistor and which has approximately the same cell size as a single PNP or NPN transistor. A ce... | 11/26/1991 |
| 5046160 | Masterslice integrated circuit device having an improved wiring structure A masterslice integrated circuit device has a basic cell array which is composed of basic cells of a first group and basic cells of a second group. An insulating layer covers the basic cells belonging to the second group, and a wiring is connected to the ... | 09/03/1991 |
| 5021856 | Universal cell for bipolar NPN and PNP transistors and resistive elements A universal cell, for use in fabricating a custom analog circuit from a standard semiconductor wafer containing a plurality of such cells, includes a semiconductor pocket of a first conductivity type having a surface. At least two regions of second conduc... | 06/04/1991 |
| 4990461 | Method of making a semiconductor integrated circuit device having resistance elements A semiconductor integrated circuit device having resistance elements having reduced fluctuation of their resistance values and a fabrication method thereof are disclosed. More definitely, a protective film made of a gate electrode material of MISFETs form... | 02/05/1991 |
| 4987326 | Semiconductor integrated circuit device having an improved common wiring arrangement In a gate array integrated circuit including a plurality of logic gate circuits having a wired-OR form, or the like, a first common combined wiring is provided for connecting the output side in such a manner that the output terminal of each logic gate cir... | 01/22/1991 |
| 4984050 | Gate-array type intergated circuit semiconductor device A gate array type integrated circuit semiconductor device includes a semiconductor substrate, in a basic cell forming portion of which are formed a plurality of impurity regions of basic circuit elements. The impurity regions form a plurality of basic cel... | 01/08/1991 |
| 4952997 | Semiconductor integrated-circuit apparatus with internal and external bonding pads A semiconductor integrated-circuit apparatus includes an electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality ... | 08/28/1990 |
| 4949149 | Semicustom chip whose logic cells have narrow tops and wide bottoms A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in... | 08/14/1990 |
| 4922136 | Master slice integrated circuit having high and low speed unit cells A semiconductor integrated circuit of the master slice system is formed by arranging internal cell groups of different operating speeds in the form of arrays respectively. The internal cell groups of different operating speeds can be interconnected with e... | 05/01/1990 |
| 4904887 | Semiconductor integrated circuit apparatus A semiconductor integrated-circuit apparatus includes an electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality ... | 02/27/1990 |
| 4898838 | Method for fabricating a poly emitter logic array A Schottky diode includes a metal layer (62) on an epitaxial region (24). The metal layer (62) is covered with a dielectric layer (64). An area (90) on the metal is exposed by opening a via (68) in the dielectric. The exposed area (90) is spaced from a bu... | 02/06/1990 |
| 4891729 | Semiconductor integrated-circuit apparatus A semiconductor integrated-circuit apparatus includes a electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality o... | 01/02/1990 |
| 4890191 | Integrated circuits In a semi-custom integrated circuit, e.g. a bipolar analogue array, underpass areas are so configured as to permit operation as capacitors by suitable configuration of a user determined interconnection pattern. Typically each underpass comprises a highly ... | 12/26/1989 |
| 4885628 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a high voltage circuit and a high-speed signal processing circuit on the same chip. The high-speed signal processing circuit is made to have a stacked construction thereby to reduce the power consumption.... | 12/05/1989 |
| 4851893 | Programmable active/passive cell structure An improved cell structure which can be programmed to have resistors, an NPN transistor or a PNP lateral transistor in a linear arrangement with an open PNP structure. The PNP collector regions are made parallel to a PNP emitter, with lightly doped resist... | 07/25/1989 |
| 4841352 | Semi-custom integrated circuit provided with standardized capacitor cells A semiconductor integrated circuit such as a semi-custom LSI includes a semiconductor substrate, a plurality of circuit elements formed on the semiconductor substrate and aligned in a plural number of lines, selected one's of the circuit elements being us... | 06/20/1989 |
| 4774559 | Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to ... | 09/27/1988 |
| 4760289 | Two-level differential cascode current switch masterslice A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite ... | 07/26/1988 |
| 4748488 | Master-slice-type semiconductor integrated circuit device A master-slice-type semiconductor integrated circuit device including basic cells, each having at least one logical circuit element, and current source cells for supplying current to the basic cells, each having at least one current source element and sep... | 05/31/1988 |
| 4737836 | VLSI integrated circuit having parallel bonding areas A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of p... | 04/12/1988 |
| 4689502 | Gate array LSI device using PNP input transistors to increase the switching speed of TTL buffers A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the ... | 08/25/1987 |
| 4675555 | IC input buffer emitter follower with current source value dependent upon connection length for equalizing signal delay In a semiconductor device including a plurality of input signal pads (P0, . . . , P7); a plurality of emitter followers (Q01, . . . , Q71) are connected to the input signal pads (P0, . . . , P7 | 06/23/1987 |
| 4641108 | Configurable analog integrated circuit An integrated circuit comprising a plurality of gain cells interspersed with a plurality of passive and active, electrically isolated components (e.g. thin-film binarily-weighted resistors and transistors). Each gain cell comprises a differential amplifie... | 02/03/1987 |
| 4613958 | Gate array chip Disclosed is a memory cell circuit for a gate array. The memory cell circuit is D.C. testable and has particular utility when employed in an integrated circuit containing "a mix of logic and array". Also disclosed is a memory array particularly adapted for use... | 09/23/1986 |
| 4564773 | Semiconductor gate array device having an improved interconnection structure In a semiconductor device having a gate array structure, a macro-cell includes more basic cells than conventional macro-cells, for preforming a logic function, whereby the density of the terminals in a direction vertical to a direction in which wiring lin... | 01/14/1986 |
| 4500906 | Multilevel masterslice LSI with second metal level programming A semiconductor device comprising a semiconductor bulk in which a plurality of basic circuit elements are formed, first interconnecting lines being formed on a first insulation layer of said semiconductor bulk, a second insulation layer formed on both sai... | 02/19/1985 |
| 4388755 | Structure for and method of manufacturing a semiconductor device by the master slice method A structure and method for manufacturing semiconductor devices by the master slice method, in which various kinds of semiconductor devices are manufactured through utilization of a common master pattern and a plurality of different kinds of selective wiri... | 06/21/1983 |
| 4295149 | Master image chip organization technique or method Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions. In a... | 10/13/1981 |
| 4278897 | Large scale semiconductor integrated circuit device A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on t... | 07/14/1981 |
| 4255672 | Large scale semiconductor integrated circuit device A large scale semiconductor integrated circuit device comprising plural transistors and resistors formed in one semiconductor substrate, and many emitter-coupled circuits formed by connecting the transistors and resistors with a double metallic layer on t... | 03/10/1981 |
| 4249193 | LSI Semiconductor device and fabrication thereof Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are ... | 02/03/1981 |
| 4207556 | Programmable logic array arrangement The programmable logic array arrangement comprises a plurality of cell units formed on a semiconductor substrate and wiring means for interconnecting the cell units. Each cell unit comprises a plurality of electronic elements such as resistors, transistor... | 06/10/1980 |
| 4080720 | High density semiconductor circuit layout An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity ... | 03/28/1978 |
