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| Number | Title | Issue Date |
| 7411277 | Semiconductor integrated circuit having shield wiring A shield wiring is provided on a boundary of a target region to be shielded of macros, an inner side of the boundary, an outer side of the boundary, or an inner side and an outer side of the boundary, each being as a black box, so as to surround the target region. T... | 08/12/2008 |
| 7348610 | Multiple layer and crystal plane orientation semiconductor substrate A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline... | 03/25/2008 |
| 7265448 | Interconnect structure for power transistors An integrated circuit according to the present invention includes first, second and third plane-like metal layers. A first transistor has a first control terminal and first and second terminals. The second terminal communicates with the first plane-like metal layer.... | 09/04/2007 |
| 7193883 | Input return path based on V/V Input circuit configurations that reduce the amount of input signal jitter caused by a common input signal return path, methods and circuits utilizing the same are provided. Input signal return path noise may be decoupled from the power for receiver circuits, for ex... | 03/20/2007 |
| 7148514 | Nitride semiconductor light emitting diode and fabrication method thereof The invention relates to a nitride semiconductor LED and a fabrication method thereof. In the LED, a first nitride semiconductor layer, an active region a second nitride semiconductor layer of a light emitting structure are formed in their order on a transparent sub... | 12/12/2006 |
| 6701509 | Integrated circuit power and ground routing An integrated circuit includes a plurality of blocks of cells, and a plurality of layers with conductors for signal and power routing. Power and ground connections for individual cells are supplied by power and ground conductors in a first layer of conduc... | 03/02/2004 |
| 6696712 | Semicustom IC having adjacent macrocells A semicustom IC including a plurality of basic cells disposed on a semiconductor substrate, a first macrocell, a second macrocell adjacent to the first macrocell, and a power supply line. The first macrocell and the second macrocell are each formed using ... | 02/24/2004 |
| 6693334 | Semiconductor integrated circuit device A shield portion 5 has such a multi-layer wiring construction comprised of three wiring layers as to correspond to a macro cell and also via contacts formed with a predetermined spacing therebetween and is supplied with a predetermined potential (for exam... | 02/17/2004 |
| 6694491 | Programmable logic array embedded in mask-programmed ASIC In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality f... | 02/17/2004 |
| 6684377 | Access cell design and a method for enabling automatic insertion of access cells into an integrated circuit design An access cell for routing current from a first cell to a second cell includes a first current path coupled to a second current path via a third current path. The third current path includes a set of three legs configured in a manner such that a first of ... | 01/27/2004 |
| 6651236 | Semiconductor integrated circuit device, and method of placement and routing for such device A semiconductor integrated circuit device fabricated with reduced size and wiring to alleviate wiring delay, and an improved placement and routing method of the building-block type for appropriate use in deep-submicron processes for fabricating such semic... | 11/18/2003 |
| 6642744 | Customizable and programmable cell array This invention discloses a customizable logic array including an array of programmable cells having a multiplicity of inputs and a multiplicity of outputs; and customized interconnections providing permanent direct interconnections among at least a plural... | 11/04/2003 |
| 6642598 | Semiconductor device In the semiconductor device according to the present invention having a plurality of function macro formation regions on the principal face of a semiconductor substrate, the plurality of the function macro formation regions include at least a first functi... | 11/04/2003 |
| 6639853 | Defect avoidance in an integrated circuit A method of using an integrated circuit with at least one defect, said method comprising the steps of determining the location of one or more defects in said integrated circuit; selecting a program to be stored on said integrated circuit, said program bei... | 10/28/2003 |
| 6633182 | Programmable gate array based on configurable metal interconnect vias A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one v... | 10/14/2003 |
| 6629309 | Mask-programmable ROM cell A structure for programming a memory cell on an integrated circuit provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In an embodiment, the structure includes... | 09/30/2003 |
| 6624492 | Semiconductor circuit device having gate array area and method of making thereof A semiconductor integrated circuit having gate array area and IP (Intellectual Property) portion. A semiconductor integrated circuit has a lower wiring region and an upper wring region on a semiconductor substrate. A gate array region is on the semiconduc... | 09/23/2003 |
| 6613611 | ASIC routing architecture with variable number of custom masks A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within t... | 09/02/2003 |
| 6603172 | Semiconductor device and method of manufacturing the same An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation. An insulating film covering the resistor film except for contact formation regions and an upper electrode fi... | 08/05/2003 |
| 6570195 | Power/ground metallization routing in a semiconductor device A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first met... | 05/27/2003 |
| 6560753 | Integrated circuit having tap cells and a method for positioning tap cells in an integrated circuit An integrated circuit includes a set of standard cells, referred to as tap cells, each having a well tap and a substrate tap for coupling a well region and a substrate region to a power source and ground, respectively. The tap cells are disposed at interv... | 05/06/2003 |
| 6545527 | Configurable electronic circuit A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configurat... | 04/08/2003 |
| 6525350 | Semiconductor integrated circuit basic cell semiconductor integrated circuit using the same A basic cell is disclosed, which is small in area and has sufficient connection flexibility. for achieving a semiconductor integrated circuit with a higher density and a reduced manufacturing cost. In a basic cell, a terminal wire, which is connected to a... | 02/25/2003 |
| 6516458 | Layout structure for integrated circuit, method and system for generating layout for CMOS circuit A layout structure and a method for generating a layout for an integrated circuit more efficiently to catch up with remarkable developments of fabrication technologies of today. In generating a layout for a CMOS circuit, a pair of p- and n-channel transis... | 02/04/2003 |
| 6513147 | Semiconductor integrated circuit device and layout method using primitive cells having indentical core designs The present invention provides a semiconductor integrated circuit device, a layout design method and apparatus thereof which enable to select an arbitrary number of grids in primitive cells and minimize the layout area. Each primitive cell is constituted ... | 01/28/2003 |
| 6504187 | Semiconductor integrated circuit and digital camera comprising the same A semiconductor capable of saving the circuit area is obtained. This semiconductor integrated circuit comprises a macro cell part having a plurality of wiring layers, an internal wire of the macro cell part formed by the wiring layers of the macro cell pa... | 01/07/2003 |
| 6496035 | Integrated circuit approach, with a serpentine conductor track for circuit configuration selection An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine c... | 12/17/2002 |
| 6484291 | Library for storing pattern shape of connecting terminal and semiconductor circuit designed with different design rules A library used for manufacturing a semiconductor IC and a method of manufacturing the semiconductor IC. The library includes structures designed with a predetermined design rule. The library has a main part including one or more circuit elements, and a co... | 11/19/2002 |
| 6480990 | Application specific integrated circuit with spaced spare logic gate subgroups and method of fabrication An application specific integrated circuit (ASIC) and method of manufacture. The ASIC includes a substrate layer, at least one metal layer and an operational block. The metal layer is formed above the substrate layer. The operational block is formed in th... | 11/12/2002 |
| 6477072 | Layout design method on semiconductor chip for avoiding detour wiring In the peripheral area of a semiconductor chip 10A, there is arranged a macro cell 51 which comprises a fuse circuit having a plurality of fuse circuit units, each of which has a fuse and outputs a signal indicating whether or not the fuse is cut off, and... | 11/05/2002 |
| 6465817 | Semiconductor integrated circuit and digital camera comprising the same A semiconductor integrated circuit capable of speeding up its operations and improving the degree of integration is obtained. This semiconductor integrated circuit comprises a macro cell part and a logic part formed around the macro cell part. The macro c... | 10/15/2002 |
| 6467074 | Integrated circuit architecture with standard blocks An integrated circuit (IC) architecture with STANDARD BLOCKs. The IC architecture forms a layout that includes a plurality of STANDARD BLOCKs, top-level cells, and hard IP blocks. The STANDARD BLOCKS form row-based or column-based STANDARD BLOCK ARRAY con... | 10/15/2002 |
| 6429521 | Semiconductor integrated circuit device and its manufacturing method On a semiconductor substrate, there are formed a first macro cell having wiring layers of three layers each formed of a metal wiring layer (for example, an aluminum wiring) and a second macro cell having wiring layers of three layers each formed of a meta... | 08/06/2002 |
| 6404226 | Integrated circuit with standard cell logic and spare gates An integrated circuit comprises an array of standard cell logic having spare gate logic dispersed therein. The spare gate logic is connectable to the standard cell logic through upper level conductors. This allows the design of an integrated circuit to be... | 06/11/2002 |
| 6388332 | Integrated circuit power and ground routing An integrated circuit includes a plurality of blocks of cells, and a plurality of layers with conductors for signal and power routing. Power and ground connections for individual cells are supplied by power and ground conductors in a first layer of conduc... | 05/14/2002 |
| 6377111 | Configurable electronic circuit A configurable electronic circuit having configuration nodes is provided. Each of the configuration nodes is coupled to corresponding first circuitry that is non-modifiable during configuration and second circuitry that is modifiable during the configurat... | 04/23/2002 |
| 6369412 | Semiconductor integrated device comprising a plurality of basic cells A plurality of first basic cells and a plurality of second basic cells are formed on a semiconductor substrate. A gate electrode of each of transistors in the first basic cell has a gate length of the minimum size. A gate electrode of each of transistors ... | 04/09/2002 |
| 6362651 | Method for fabricating PLDs including multiple discrete devices formed on a single chip A method for producing multi-device PLDs wherein a wafer layout architecture includes device-linking conductors that allow a wafer to be diced into both single-device chips and multi-device chips. A multi-device chip is a single chip that includes two or ... | 03/26/2002 |
| 6335640 | Semiconductor integrated circuit device with its layout designed by the cell base method A feedthrough cell or cap cell includes a basic pair of a gate electrode and pairs of P-type diffused regions and N-type diffused regions. With this structure, even if a design change arises after the completion of a layout plan, a logic circuit can be fo... | 01/01/2002 |
| 6334207 | Method for designing application specific integrated circuits An ASIC design methodology in which portions of the ASIC are implemented in silicon or other suitable semiconductor technology at an early stage in the design flow through the use of a series of interim devices. The invention provides a method in which ad... | 12/25/2001 |
