Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442985 | Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed t... | 10/28/2008 |
| 7442998 | Non-volatile memory device A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell... | 10/28/2008 |
| 7442997 | Three-dimensional memory cells The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-... | 10/28/2008 |
| 7432204 | Wafer and the manufacturing and reclaiming methods thereof A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having... | 10/07/2008 |
| 7419870 | Method of manufacturing a flash memory device Provided is a method of manufacturing a flash memory device. In the method, after forming a cell string and source/drain selection transistors, it forms a first oxide film in which a sidewall oxide film and a buffering oxide film are stacked, a nitride film, and a s... | 09/02/2008 |
| 7413953 | Method of forming floating gate array of flash memory device The method of forming a floating gate array of a flash memory device includes: (a) sequentially forming a tunnel oxide film, a floating gate forming film, a capping oxide film and a first nitride film on a semiconductor substrate with an active device region defined... | 08/19/2008 |
| 7410869 | Method of manufacturing a semiconductor device In a method of manufacturing a semiconductor device such as a flash memory device, an insulating pattern having an opening is formed to partially expose a surface of a substrate. A first silicon layer is formed on the exposed surface portion of the substrate and the... | 08/12/2008 |
| 7411239 | Nand flash memory devices and methods of fabricating the same A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed ... | 08/12/2008 |
| 7397078 | Non-volatile semiconductor memory A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor... | 07/08/2008 |
| 7391073 | Non-volatile memory structure and method of fabricating non-volatile memory A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer.... | 06/24/2008 |
| 7390716 | Method of manufacturing flash memory device A method of manufacturing a flash memory device. An etch process for controlling the effective field height of isolation layers is performed using a dry etch process on condition that an excessive amount of polymer is generated, thus forming first spacers on sidewal... | 06/24/2008 |
| 7378705 | Single-poly EEPROM cell with lightly doped MOS capacitors An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. Th... | 05/27/2008 |
| 7368341 | Semiconductor circuit arrangement with trench isolation and fabrication method An explanation is given of, inter alia, a circuit arrangement containing a trench which penetrates through a charge-storing layer (18) and a doped semiconductor layer (14). The trench simultaneously fulfils a multiplicity of functions, namely an insula... | 05/06/2008 |
| 7368781 | Contactless flash memory array A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on a substrate. An insulating layer is then deposited over the active regions, and a portion of the insulati... | 05/06/2008 |
| 7365388 | Embedded trap direct tunnel non-volatile memory The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric consta... | 04/29/2008 |
| 7341911 | Method of making EEPROM transistor pairs for block alterable memory A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain... | 03/11/2008 |
| 7339231 | Semiconductor device and an integrated circuit card There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memor... | 03/04/2008 |
| 7323743 | Floating gate A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A ... | 01/29/2008 |
| 7314798 | Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr... | 01/01/2008 |
| 7315056 | Semiconductor memory array of floating gate memory cells with program/erase and select gates A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an el... | 01/01/2008 |
| 7307332 | Semiconductor device and method for fabricating the same The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the sidewall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate ele... | 12/11/2007 |
| 7304344 | Integrated circuit having independently formed array and peripheral isolation dielectrics The invention comprises a method of forming an integrated circuit, the method comprising: (1) forming a first dielectric layer disposed outwardly from a semiconductor substrate; (2) forming a first intermediate structure outwardly from the a dielectric layer, the fi... | 12/04/2007 |
| 7301804 | NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing... | 11/27/2007 |
| 7291546 | Method and apparatus for reducing charge loss in a nonvolatile memory cell A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate desi... | 11/06/2007 |
| 7291881 | Bit line structure and method of fabrication The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which conta... | 11/06/2007 |
| 7291882 | Programmable and erasable digital switch device and fabrication method and operating method thereof A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge sto... | 11/06/2007 |
| 7274067 | Service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu... | 09/25/2007 |
| 7274063 | Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions In a nonvolatile memory cell having at least two floating gates, each floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2... | 09/25/2007 |
| 7271438 | Self-aligned silicide for word lines and contacts An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer, a source region formed in a semiconductor ... | 09/18/2007 |
| 7262456 | Bit line structure and production method thereof The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled wi... | 08/28/2007 |
| 7253054 | One time programmable EPROM for advanced CMOS technology A one time programmable (OTP) electrically programmable read only memory (EPROM) transistor (100) having an increased breakdown voltage (BVdss) is disclosed. The increased breakdown voltage reduces the probability that the OTP EPROM (100) will breakdow... | 08/07/2007 |
| 7242049 | Memory device A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the... | 07/10/2007 |
| 7221017 | Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A float... | 05/22/2007 |
| 7211866 | Scalable self-aligned dual floating gate memory cell array and methods of forming the array An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then ... | 05/01/2007 |
| 7205602 | Method to improve the coupling ratio of top gate to floating gate in flash A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion w... | 04/17/2007 |
| 7202544 | Giant magnetoresistance structure The present invention relates to a method for producing a GMR structure in which a metallic multiple layer is applied onto a carrier and in which the metallic multiple layer is patterned to produce the GMR structure, the carrier having a structure before the metalli... | 04/10/2007 |
| 7196370 | Nonvolatile semiconductor memory device having trench-type isolation region, and method of fabricating the same A nonvolatile semiconductor memory device includes a memory cell array region including a plurality of NAND cells, each NAND cell having a plurality of memory cell transistors, and which are arranged in series, and a plurality of select transistors. A trench-type is... | 03/27/2007 |
| 7190019 | Integrated circuits with openings that allow electrical contact to conductive features having self-aligned edges A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feat... | 03/13/2007 |
| 7190023 | Semiconductor integrated circuit having discrete trap type memory cells A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a ... | 03/13/2007 |
| 7183607 | Non-volatile memory structure A non-volatile memory structure including a substrate, a first memory cell row, a first source/drain region, and a second source/drain region is described. The first memory cell row is disposed on the substrate and includes a plurality of memory cells, two select ga... | 02/27/2007 |
