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| Number | Title | Issue Date |
| 7442997 | Three-dimensional memory cells The present invention discloses a three-dimensional memory (3D-M) with polarized 3D-ROM (three-dimensional read-only memory) cells. Polarized 3D-ROM can ensure a larger unit array and therefore, a better integratibility. The present invention further discloses a 3D-... | 10/28/2008 |
| 7365355 | Programmable matrix array with phase-change material A phase-change material is proposed for coupling interconnect lines an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer between the phase change material and at least one of the lines. The matrix ... | 04/29/2008 |
| 7358120 | Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROM A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell... | 04/15/2008 |
| 7358562 | NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga... | 04/15/2008 |
| 7321153 | Semiconductor memory device and corresponding programming method A semiconductor cell includes, within a substrate region, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, ... | 01/22/2008 |
| 7268389 | Nonvolatile semiconductor memory A nonvolatile semiconductor memory device includes diffusion layers formed in a semiconductor substrate, a gate insulating film formed on at least a portion of a channel region between the diffusion layers in the semiconductor substrate, and a control gate formed on... | 09/11/2007 |
| 7256444 | Local SONOS-type nonvolatile memory device and method of manufacturing the same Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each... | 08/14/2007 |
| 7227233 | Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell... | 06/05/2007 |
| 7151051 | Interconnect structure for an integrated circuit and method of fabrication An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful w... | 12/19/2006 |
| 7126196 | Self-testing printed circuit board comprising electrically programmable three-dimensional memory The electrically programmable three-dimensional memory (EP-3DM) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, EP-3DM has minimum impact to the layout of the CUT. Apparently, CUT with integra... | 10/24/2006 |
| 6704922 | Correcting method of mask and mask manufactured by said method According to a first aspect of the present invention, there is provided a method of correcting a mask for a data program of a read only memory, comprising selecting an optional data from a data map comprising first data and second data, the optional data ... | 03/09/2004 |
| 6700176 | MOSFET anti-fuse structure and method for making same An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain ex... | 03/02/2004 |
| 6700151 | Reprogrammable non-volatile memory using a breakdown phenomena in an ultra-thin dielectric A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store inform... | 03/02/2004 |
| 6699757 | Method for manufacturing embedded non-volatile memory with sacrificial layers A process uses two layers of polysilicon for fabricating high-density nonvolatile memory, such as mask ROM or SONOS memory, integrated with advanced peripheral logic on a single chip. The method includes covering a gate dielectric layer with a sacrificial... | 03/02/2004 |
| 6693309 | Mask ROM and method for manufacturing the same A mask ROM and a method for manufacturing such a mask ROM are provided. Here, the mask ROM can be effective to obtain a product that corresponds to each user's specification, where the same aluminum reticle is used even though each user uses different spe... | 02/17/2004 |
| 6687154 | Highly-integrated flash memory and mask ROM array architecture A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source... | 02/03/2004 |
| 6675580 | PV/thermal solar power assembly A flexible solar power assembly (2) includes a flexible photovoltaic device (16) attached to a flexible thermal solar collector (4). The solar power assembly can be rolled up for transport and then unrolled for installation on a surface, such as the roof ... | 01/13/2004 |
| 6677206 | Non-volatile high-performance memory device and relative manufacturing process A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the ga... | 01/13/2004 |
| 6673682 | Methods of fabricating high density mask ROM cells Methods for making integrated circuit devices, such as high density memory devices and memory devices exhibiting dual bits per cell, include forming multiple oxide fences on a semiconductor substrate between multiple polybars. The oxide fences create a ho... | 01/06/2004 |
| 6674661 | Dense metal programmable ROM with the terminals of a programmed memory transistor being shorted together A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and a ground conection, with each m... | 01/06/2004 |
| 6670247 | Method of fabricating mask read only memory A method of fabricating a mask read only memory. Embedded bit line are formed in a substrate. A gate dielectric layer and a word line are formed on the substrate. The word line is perpendicular to the bit lines. The substrate under the word line and betwe... | 12/30/2003 |
| 6671040 | Programming methods and circuits for semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric A programming circuit includes a wordline decoder, an adjustable voltage generator, and a column transistor. The programming circuit is useful in programming a memory cell comprised of a select transistor and a data storage element. The data storage eleme... | 12/30/2003 |
| 6667902 | Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage cur... | 12/23/2003 |
| 6665207 | ROM embedded DRAM with dielectric removal/short A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper con... | 12/16/2003 |
| 6661691 | Interconnection structure and methods Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least so... | 12/09/2003 |
| 6660589 | Semiconductor devices and methods for fabricating the same Semiconductor devices and methods for fabricating the same include a device isolation layer formed at a predetermined region of a semiconductor substrate to define a cell active region, a resistor active region, and an MROM active region. The device furth... | 12/09/2003 |
| 6653692 | Double access path mask ROM cell structure The present invention discloses a double access path mask read-only memory cell array structure, characterized in that the stored data is accessed simultaneously through two access paths disposed on both sides of a memory cell array structure. The reliabi... | 11/25/2003 |
| 6653671 | Semiconductor device A semiconductor device has a dummy pattern including an underlying layer which is formed on a semiconductor substrate and in which a plurality of word lines from N-2 to N+2 are arranged in parallel, a plurality of blocks each of which has a plurality of d... | 11/25/2003 |
| 6645816 | Fabricating memory device having buried source/drain region and fabrication thereof A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barri... | 11/11/2003 |
| 6646312 | Semiconductor memory device with bit lines having reduced cross-talk A semiconductor memory device is fabricated to have a multi-layered structure on a semiconductor substrate. The semiconductor memory device includes ground lines, which are formed in a first conductive layer; bit lines, which are formed in a second conduc... | 11/11/2003 |
| 6642587 | High density ROM architecture A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of informati... | 11/04/2003 |
| 6642118 | Method for eliminating polysilicon residue by fully converting the polysilicon into silicon dioxide A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of ... | 11/04/2003 |
| 6621129 | MROM memory cell structure for storing multi level bit information A MROM memory cell structure for storing multi level bit information is disclosed. First of all, a substrate is provided. The substrate has first and second trenches therein, wherein the first trench is deeper than second trench. A conformnal dielectric l... | 09/16/2003 |
| 6617633 | Vertical read-only memory and fabrication thereof A vertical read-only memory (ROM) is provided, which includes a gate on a substrate, a source/drain at the bottom of a trench in the substrate, a polysilicon bit-line in the trench, and a dielectric layer separating the polysilicon bit-line and the side-w... | 09/09/2003 |
| 6614080 | Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposi... | 09/02/2003 |
| 6593624 | Thin film transistors with vertically offset drain regions There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electro... | 07/15/2003 |
| 6590266 | 2-bit mask ROM device and fabrication method thereof A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate s... | 07/08/2003 |
| 6573573 | Mask ROM and method for fabricating the same Mask ROM and method for fabricating the same, are disclosed, which is operative at a fast speed and a low voltage, including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, conductive layer patterns formed on the ... | 06/03/2003 |
| 6573574 | Cell array region of a NOR-type mask ROM device and fabricating method therefor In a cell array region of a NOR-type mask ROM device and a fabricating method therefor, following formation of a plurality of word lines parallel to one another on a semiconductor substrate, a plurality of sub-bit lines intersecting the top portion of the... | 06/03/2003 |
| 6570235 | Cells array of mask read only memory A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that ... | 05/27/2003 |
