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| Number | Title | Issue Date |
| 7388274 | Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an act... | 06/17/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7320923 | SRAM cell A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable... | 01/22/2008 |
| 7304352 | Alignment insensitive D-cache cell A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one rea... | 12/04/2007 |
| 7256463 | Semiconductor device having SOI structure including a load resistor of an sram memory cell It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source r... | 08/14/2007 |
| 7122850 | Semiconductor device having local interconnection layer and etch stopper pattern for preventing leakage of current A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor... | 10/17/2006 |
| 6690071 | Semiconductor device using junction leak current A first well of a first conductivity type is formed in a partial region of the surface layer of a semiconductor substrate. A MOS transistor is formed in the first well. The MOS transistor has a gate insulating film, a gate electrode, and first and second ... | 02/10/2004 |
| 6635936 | SRAM layout for relaxing mechanical stress in shallow trench isolation technology An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a... | 10/21/2003 |
| 6624526 | Compact SRAM cell incorporating refractory metal-silicon-nitrogen resistive elements and method for fabricating A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched ... | 09/23/2003 |
| 6586310 | High resistivity film for 4T SRAM The present invention provides a method of manufacturing a resistor for use in a memory element and a semiconductor device employing the resistor. The method of manufacturing may comprise forming a dielectric layer over an active region of a semiconductor... | 07/01/2003 |
| 6563177 | Semiconductor memory device having a trench and a gate electrode vertically formed on a wall of the trench A semiconductor memory device includes a trench type SRAM(Static Random Access Memory) cell having a higher integration than a stack type SRAM. The SRAM cell memory device is provided with a trench formed in a semiconductor substrate and having four side ... | 05/13/2003 |
| 6489213 | Method for manufacturing semiconductor device containing a silicon-rich layer A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich a... | 12/03/2002 |
| 6482693 | Methods of forming diodes Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 11/19/2002 |
| 6458655 | Method of manufacturing semiconductor device and flash memory A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an ... | 10/01/2002 |
| 6455904 | Loadless static random access memory device and method of manufacturing same A plurality of p wells and a plurality of n wells are formed in a p-type semiconductor substrate having a memory portion and a peripheral circuit portion. Next, a resist pattern is formed on the semiconductor substrate. The resist pattern has apertures wh... | 09/24/2002 |
| 6455918 | Integrated circuitry Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 09/24/2002 |
| 6440790 | Method of making semiconductor device having an insulating film positioned between two similarly shaped conductive films A plurality of conductive films are formed on a semiconductor substrate with an insulating film sandwiched between the adjacent conductive films, and at least two of the plurality of conductive films are patterned simultaneously in the same shape. Selecte... | 08/27/2002 |
| 6432766 | Method of fabricating a SRAM device The present invention comprises an improved method of forming the source voltage lines, connection lines, and high load resistors for use in HLR SRAM devices. The source voltage lines, connection lines, and high load resistors are formed from a single pol... | 08/13/2002 |
| 6432764 | Methods of forming resistors Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 08/13/2002 |
| 6423606 | Semiconductor processing methods, methods of forming a resistor and methods of forming a diode Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 07/23/2002 |
| 6372641 | Method of forming self-aligned via structure A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.... | 04/16/2002 |
| 6369428 | Polysilicon load for 4T SRAM operating at cold temperatures This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The pro... | 04/09/2002 |
| 6362039 | Self-aligned resistor and local interconnect A method is provided for combining the process steps for forming a resistor and interconnect into one process layer, thus eliminating the need for at least two mask steps. An oxide layer is formed over a region of a polysilicon layer in which the resistor... | 03/26/2002 |
| 6352888 | Method of fabricating SRAM cell having a field region A static random access memory (SRAM) cell includes first and second load devices, first and second access transistors, first and second drive transistors, and two bit lines. The SRAM includes a substrate; an active region in the substrate, the active regi... | 03/05/2002 |
| 6350645 | Strapping via for interconnecting integrated circuit structures A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a cont... | 02/26/2002 |
| 6340834 | Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 01/22/2002 |
| 6340835 | Method of making a resistor, method of making a diode, and SRAM circuitry and other integrated circuitry Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection... | 01/22/2002 |
| 6310397 | Butted contact resistance of an SRAM by double VCC implantation Form a butted contact in an SRAM memory device by exposing a contact region on the surface of a doped semiconductor substrate and a conductor stack above a field oxide region on the surface of the substrate. Form an interpolysilicon silicon oxide dielectr... | 10/30/2001 |
| 6303422 | Semiconductor memory and manufacturing method thereof A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of ... | 10/16/2001 |
| 6300180 | Method for forming an integrated circuit having improved polysilicon resistor structures A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interco... | 10/09/2001 |
| 6297083 | Method of forming four transistor SRAM cell having a resistor A device structure and a method of forming the structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by using amphorous () silicon between metal barrier layers, suc... | 10/02/2001 |
| 6285088 | Compact memory circuit An integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. In one embodiment the strapping 750, 752, 756 is placed between the moats 706,724 of transistors that compose cross-coupled in... | 09/04/2001 |
| 6271569 | Semiconductor device having memory cells and method of manufacturing the same According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node ... | 08/07/2001 |
| 6268240 | Static semiconductor memory device capable of enhancing access speed In a static memory cell including first and second drive MOS transistors, first and second MOS transfer transistors and first and second load elements, the drain of the first drive MOS transistor and the source of the first transfer MOS transistor are for... | 07/31/2001 |
| 6242781 | Resistor constructions A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pu... | 06/05/2001 |
| 6239458 | Polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor This is a method of forming an SRAM transistor cell on a well in a doped semiconductor substrate. Form a gate oxide layer and a split gate layer with buried contact regions in the well and openings through the split gate layer and the gate oxide layer to ... | 05/29/2001 |
| 6238993 | Polysilicon load for 4T SRAM operation at cold temperatures This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The pro... | 05/29/2001 |
| 6238962 | Method of fabricating static random access memory cell with vertically arranged drive transistors A method of fabricating an SRAM cell having a first conductivity type substrate includes the steps of forming a well of a second conductivity type in the first conductivity type substrate, forming a first active region of a first access transistor and a s... | 05/29/2001 |
| 6236117 | Semiconductor memory device including shunt interconnection A semiconductor device including a shunt interconnection which operates at higher speed and permits high density integration is provided. In the semiconductor device including the shunt interconnection, a shunt connection region for a word line and a firs... | 05/22/2001 |
| 6232194 | Silicon nitride capped poly resistor with SAC process A new method of forming a polysilicon resistor having precisely controlled resistance by using a thin silicon nitride cap over the polysilicon resistor is described. A dielectric layer is provided on a semiconductor substrate. A polysilicon layer is depos... | 05/15/2001 |
