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| Number | Title | Issue Date |
| 7423290 | Electro-optical device and driving method for the same A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected ... | 09/09/2008 |
| 7414266 | Semiconductor device and manufacturing method thereof A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. By performing the formation of the pixel electrode 127, the source region 123 and the drain regio... | 08/19/2008 |
| 7394098 | Thin film transistor, its manufacture method and display device On an insulating substrate, a first insulating buffer layer, a heat accumulating-light shielding layer having at least a silicon layer on the surface thereof, a second insulating buffer layer and a first silicon layer are laminated in the order recited from the bott... | 07/01/2008 |
| 7352005 | Electro-optical device, manufacturing method thereof, and electronic apparatus The disclosure is directed to an electro-optical device and manufacturing method. In one example, a storage capacitor is disposed above a data line. The storage capacitor has a stacked structure of a fixed-potential electrode, a dielectric layer, and a pixel-potenti... | 04/01/2008 |
| 7345308 | Solid-state imaging device A solid-state imaging device includes: a photoelectric conversion element; a pixel region including a modulation part formed adjacent to the photoelectric conversion element; and a peripheral region in which a peripheral circuit including a driving circuit driving t... | 03/18/2008 |
| 7339189 | Substrate for semiconductor device, method of manufacturing substrate for semiconductor device, substrate for electro-optical device, electro-optical device, and electronic apparatus A substrate for a semiconductor device includes a substrate, a thin film transistor that is provided on the substrate, a wiring line that is provided above the thin film transistor, an interlayer insulating film that electrically isolates the wiring line from at lea... | 03/04/2008 |
| 7335923 | Electroluminescence display device An electroluminescence display device that includes a thin film transistor layer formed on a substrate, at least one insulating layer formed on the thin film transistor layer, and a pixel layer, disposed on the insulating layer and including a first electrode layer,... | 02/26/2008 |
| 7329901 | Thin-film semiconductor device, electro-optical device, and electronic apparatus A thin-film semiconductor device includes, on the same substrate, a thin-film transistor, in which an active layer, a gate insulating film, and a gate electrode are laminated, and a capacitive element, in which a first electrode formed using a semiconductor film for... | 02/12/2008 |
| 7282769 | Thin film transistor device and method of making the same The electronic device comprises a thin-film transistor (10) and can be obtained from two substrates (1, 11). In order to preclude delamination at a non-adhesive interface between a metal pattern (24, 29) and an organic layer (4), the meta... | 10/16/2007 |
| 7247883 | Thin film transistor having LDD structure A thin film transistor having a LDD structure that may improve its channel reliability and output characteristics. A semiconductor layer comprises source/drain regions, a channel region positioned between the source/drain regions, and an LDD region positioned betwee... | 07/24/2007 |
| 7238554 | Simultaneous planar and non-planar thin-film transistor processes A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT havi... | 07/03/2007 |
| 7115906 | Thin film transistor array and fabricating method thereof A thin film transistor array including a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, an etch barrier layer and a plurality of pixel electrodes is provided. The scan lines and the data lines are disposed over... | 10/03/2006 |
| 6849958 | Semiconductor latches and SRAM devices A new Static Random Access Memory (SRAM) cell using Thin Film Transistors (TFT) is disclosed. In a first embodiment, an SRAM cell comprises a strong inverter and a strong access device constructed on a semiconductor substrate layer, and a weak inverter and a weak ac... | 02/01/2005 |
| 6806918 | Active matrix substrate and method of manufacturing the same A method of manufacturing an active matrix substrate comprises forming a plurality of elements on an element formation substrate, forming wirings on a final substrate, transferring some elements selected from the elements, and selectively connecting some elements to... | 10/19/2004 |
| 6689649 | Methods of forming transistors An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each cond... | 02/10/2004 |
| 6649935 | Self-aligned, planarized thin-film transistors, devices employing the same A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect... | 11/18/2003 |
| 6620659 | Merged logic and memory combining thin film and bulk Si transistors The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two k... | 09/16/2003 |
| 6573549 | Dynamic threshold voltage 6T SRAM cell An embodiment of the instant invention is a memory device comprising: a memory cell including: a first transistor (108 of FIG. 1) having a control electrode, a current path, and a backgate/body connection electrically connected to the control electrode of... | 06/03/2003 |
| 6501178 | Semiconductor device In a semiconductor device, a first conductive layer (2) is located on a semiconductor substrate (14) through an insulating film (13a) and beneath a first insulating layer (13f). On the first insulating layer (13f) is formed a second conductive layer (8) f... | 12/31/2002 |
| 6479332 | Methods of forming integrated circuitry An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each cond... | 11/12/2002 |
| 6440790 | Method of making semiconductor device having an insulating film positioned between two similarly shaped conductive films A plurality of conductive films are formed on a semiconductor substrate with an insulating film sandwiched between the adjacent conductive films, and at least two of the plurality of conductive films are patterned simultaneously in the same shape. Selecte... | 08/27/2002 |
| 6407420 | Integrated circuit device having line width determined by side wall spacer provided in openings formed in insulating film for connection conductors According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode... | 06/18/2002 |
| 6384454 | Process for manufacturing integrated circuit SRAM An SRAM cell is described which has a reduced cell area, and a reduced processing cost from conventional SRAM's. A fabrication process is described where self-aligned contacts to substrate active area and contact to a first layer of polysilicon are formed... | 05/07/2002 |
| 6376287 | Method of making field effect A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the ... | 04/23/2002 |
| 6323072 | Method for forming semiconductor thin film A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-li... | 11/27/2001 |
| 6306696 | Methods of forming integrated circuitry methods of forming thin film transistors, integrated circuitry and thin film transistors An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each cond... | 10/23/2001 |
| 6303966 | SRAM cell having overlapping access transistor and drive transistor gates An SRAM cell and method for fabricating the same including first and second access transistors, first and second drive transistors, and first and second load resistors. A first terminal of the first access transistor, a gate terminal of the second drive t... | 10/16/2001 |
| 6291276 | Cross coupled thin film transistors and static random access memory cell A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first T... | 09/18/2001 |
| 6271063 | Method of making an SRAM cell and structure A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistor... | 08/07/2001 |
| 6271542 | Merged logic and memory combining thin film and bulk Si transistors The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two k... | 08/07/2001 |
| 6268627 | Semiconductor device having impurity regions with varying impurity concentrations In an access transistor formed on a silicon substrate, its drain region is formed of n- type and n+ type drain regions and its source region is formed of n- type and n+ type source regions. In a driver transisto... | 07/31/2001 |
| 6255146 | Thin film transistor and a method of manufacturing thereof According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using... | 07/03/2001 |
| 6251713 | Method of making an SRAM storage cell with N channel thin film transistor load devices An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source short... | 06/26/2001 |
| 6251714 | Method of making thin film field effect transistors A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the ... | 06/26/2001 |
| 6235562 | Method of making field effect transistors A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the ... | 05/22/2001 |
| 6229212 | Integrated circuitry and thin film transistors An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each cond... | 05/08/2001 |
| 6222214 | Plug structure and process for forming stacked contacts and metal contacts on static random access memory thin film transistors A method for fabricating a novel plug structure for low resistance ohmic stacked contacts and at the same time forming metal contacts to devices on a SRAM cell was achieved. The method involved forming electrically conductive plugs in the stacked contact ... | 04/24/2001 |
| 6188085 | Thin film transistor and a method of manufacturing thereof According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using... | 02/13/2001 |
| 6174764 | Process for manufacturing integrated circuit SRAM An SRAM cell is described which has a reduced cell area, and a reduced processing cost from conventional SRAM's. A fabrication process is described where self-aligned contacts to substrate active area and contact to a first layer of polysilicon are formed... | 01/16/2001 |
| 6150201 | Methods of forming top-gated thin film field effect transistors A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the ... | 11/21/2000 |
