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| Number | Title | Issue Date |
| 7394135 | Dual source MOSFET for low inductance synchronous rectifier A dual source MOSFET comprises a large number of cells diffused into a substrate. The cells are divided into two regions with separate sources and gates but having a common drain connection, the substrate. It is preferred that the source regions be highly interdigit... | 07/01/2008 |
| 7332780 | Inverter, semiconductor logic circuit, static random access memory and data latch circuit A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type ... | 02/19/2008 |
| 7323735 | Method of manufacturing semiconductor integrated circuit device having capacitor element In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) ... | 01/29/2008 |
| 7304352 | Alignment insensitive D-cache cell A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one rea... | 12/04/2007 |
| 7244977 | Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory d... | 07/17/2007 |
| 7192814 | Method of forming a low capacitance semiconductor device and structure therefor In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator. ... | 03/20/2007 |
| 7190031 | Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor laye... | 03/13/2007 |
| 7161215 | Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor laye... | 01/09/2007 |
| 7006369 | Design and use of a spacer cell to support reconfigurable memories The present invention provides a method and apparatus for reconfiguring a memory array. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and secon... | 02/28/2006 |
| 6700166 | Semiconductor memory device with improved soft-error resistance A memory cell has two cross-coupled inverters each formed from a load transistor and a drive transistor. In the memory cell, the gates of the load transistor and the drive transistor are electrically coupled to the same gate line having a poly-metal gate ... | 03/02/2004 |
| 6693360 | Static type semiconductor memory device A memory cell of a static type semiconductor memory device includes a gate electrode of an MOS transistor formed on a main surface of semiconductor substrate via an insulator film, an interlayer insulator film covering the gate electrode, a set of contact... | 02/17/2004 |
| 6690030 | Semiconductor device with negative differential resistance characteristics A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or "thinned" at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon o... | 02/10/2004 |
| 6686633 | Semiconductor device, memory cell, and processes for forming them A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at lea... | 02/03/2004 |
| 6677649 | SRAM cells with two P-well structure Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymm... | 01/13/2004 |
| 6670262 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed. A silicon oxide film, a polysilicon film and a silicon oxide film are formed in the order named on a silicon substrate. Then, the ... | 12/30/2003 |
| 6670642 | Semiconductor memory device using vertical-channel transistors The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of... | 12/30/2003 |
| 6664603 | Semiconductor device, memory system and electronic apparatus A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes a first gate-gate electrode layer and a first drain-... | 12/16/2003 |
| 6661063 | Semiconductor integrated circuit device Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, an... | 12/09/2003 |
| 6657885 | Static semiconductor memory device A memory cell includes an n well and a p well. A word line is provided over memory cell and n well and p well are arranged in a direction in which word line extends. A single word line is provided for each memory cell and formed of metal.... | 12/02/2003 |
| 6657243 | Semiconductor device with SRAM section including a plurality of memory cells A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transis... | 12/02/2003 |
| 6653696 | Semiconductor device, memory system, and electronic instrument The present invention provides a semiconductor device including a first gate--gate electrode layer located in a first conductive layer and including gate electrodes of a first load transistor and a first driver transistor and a second gate--gate electrode... | 11/25/2003 |
| 6653695 | Semiconductor device with an improved gate electrode pattern Disclosed is a semiconductor device using a gate electrode such as an SRAM, wherein the electrode pattern is a formed with fidelity to a reticle pattern through no complicated layout design. The gate electrode pattern is formed in an area smaller than tha... | 11/25/2003 |
| 6649456 | SRAM cell design for soft error rate immunity A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar stor... | 11/18/2003 |
| 6650143 | Field programmable gate array based upon transistor gate oxide breakdown A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and a second terminal, the first terminal connected to a colum... | 11/18/2003 |
| 6646305 | Grounded body SOI SRAM cell A semiconductor memory device comprising: an SOI substrate having a thin silicon layer on top of a buried insulator; and an SRAM comprising four NFETs and two PFETs located in the thin silicon layer, each the NFET and PFET having a body region between a s... | 11/11/2003 |
| 6642555 | Semiconductor memory device A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where chann... | 11/04/2003 |
| 6642588 | Latch-up prevention for memory cells An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. T... | 11/04/2003 |
| 6635937 | Semiconductor integrated circuit device To improve performance, a capacitor is provided between storage nodes of an SRAM and a device having an analog capacitor on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and... | 10/21/2003 |
| 6635966 | Method for fabricating SRAM cell A method of fabricating the SRAM cell is disclosed. The method includes forming a gate on a substrate, forming an oxidation barrier film on side portions of the gate, oxidizing the resultant structure by using an oxidation process to form an oxide film on... | 10/21/2003 |
| 6636075 | Semiconductor integrated circuit and its fabrication method An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type... | 10/21/2003 |
| 6632750 | Manufacturing method of semiconductor integrated circuit device Described is a manufacturing method of a semiconductor integrated circuit device by depositing a silicon nitride film to give a uniform thickness over the main surface of a semiconductor wafer having a high pattern density region and a low pattern density... | 10/14/2003 |
| 6627490 | Semiconductor device and method for fabricating the same A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provi... | 09/30/2003 |
| 6628536 | Semiconductor memory device A semiconductor memory device with a high-capacity memory cell array includes a plurality of global word lines per memory cell row of the memory cell array. The global word lines are formed in two wiring layers (upper and lower layers). This substantially... | 09/30/2003 |
| 6627528 | Semiconductor device and its manufacturing process Gate electrodes in an inverter section and a transfer section are formed only on element areas, and connected to each other by means of local interconnection layers. As a result, a memory cell of a very small size but a large capacity can be formed withou... | 09/30/2003 |
| 6627960 | Semiconductor data storage apparatus An SRAM memory cell includes two inverters connected in complement with each other. Each inverter includes one NMOS transistor and one PMOS transistor. The gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the... | 09/30/2003 |
| 6624459 | Silicon on insulator field effect transistors having shared body contact Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do... | 09/23/2003 |
| 6621127 | Semiconductor memory device with miniaturization improvement An isolating insulation film and a P type active region defined by the isolating insulation film are formed on a semiconductor substrate. Then, an access transistor gate electrode, driver transistor gate electrodes, and a dummy gate electrode are formed. ... | 09/16/2003 |
| 6613634 | Method of manufacturing a semiconductor device using oblique ion injection Upon formation, by oblique ion injection, of a pocket ion region in a p channel type MISFET forming region (n type well) constituting an SRAM, the p channel type MISFET forming region is disposed at a distance from a resist film formed over an n channel t... | 09/02/2003 |
| 6613617 | Cross-diffusion resistant dual-polycide semiconductor structure and method A dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. A conductive layer is formed over a polysilicon layer having a first region doped with a first dopant and a second region adjoining the first re... | 09/02/2003 |
| 6603178 | Semiconductor integrated circuit device and method of manufacture thereof Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, an... | 08/05/2003 |
