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| Number | Title | Issue Date |
| 7425744 | Fabricating logic and memory elements using multiple gate layers Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material ... | 09/16/2008 |
| 7417302 | Semiconductor device and method of manufacturing the same In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first ... | 08/26/2008 |
| 7417288 | Substrate solution for back gate controlled SRAM with coexisting logic devices A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devic... | 08/26/2008 |
| 7411238 | Semiconductor integrated circuit device and a method of manufacturing the same In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN fi... | 08/12/2008 |
| 7408231 | SRAM memory semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same... | 08/05/2008 |
| 7394119 | Metal oxide semiconductor (MOS) type semiconductor device and having improved stability against soft errors A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type t... | 07/01/2008 |
| 7382026 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 06/03/2008 |
| 7375401 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 05/20/2008 |
| 7372105 | Semiconductor device with power supply impurity region A semiconductor device in which by fixing a well at a predetermined potential via a contact within a memory cell, latch-up immunity is improved without accompanying increase in the area of the memory cell, and of which manufacture is facilitated, and a manufacturing... | 05/13/2008 |
| 7365398 | Compact SRAMs and other multiple transistor structures A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one ... | 04/29/2008 |
| 7358131 | Methods of forming SRAM constructions The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 04/15/2008 |
| 7358575 | Method of fabricating SRAM device A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on... | 04/15/2008 |
| 7358556 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 04/15/2008 |
| 7323735 | Method of manufacturing semiconductor integrated circuit device having capacitor element In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) ... | 01/29/2008 |
| 7320923 | SRAM cell A method for forming a resistor of high value in a semiconductor substrate including forming a stack of a first insulating layer, a first conductive layer, a second insulating layer, and a third insulating layer, the third insulating layer being selectively etchable... | 01/22/2008 |
| 7309890 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 12/18/2007 |
| 7306984 | Method of manufacture of a semiconductor integrated circuit device including a plurality of columnar laminates having different spacing in different directions For improving the filing properties between vertical MISFETs constituting a SRAM memory cell, the vertical MISFETs are formed over horizontal drive MISFETs and transfer MISFETs, and they are disposed with a narrow pitch in the Y direction and a wide pitch in the X d... | 12/11/2007 |
| 7307871 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ... | 12/11/2007 |
| 7285832 | Multiport single transistor bit cell A multiport memory cell (200, 300, 600) includes a first word line (WL1) coupled to a gate electrode of a first transistor (201, 301, 601). A second word line (WL2) is coupled to a gate electrode of a second transistor (202, 302, 602 | 10/23/2007 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7279755 | SRAM cell with improved layout designs A 6T SRAM cell includes a first inverter having a first pull-up transistor and a first pull-down transistor serially coupled between a supply source and a complementary supply source, and a second inverter cross-coupled with the first inverter having a second pull-u... | 10/09/2007 |
| 7271451 | Memory cell structure A memory structure that reduces soft-errors for us in CMOS devices is provided. The memory cell layout utilizes transistors oriented such that the source-to-drain axis is parallel a shorted side of the memory cell. The dimensions of the memory cell are such that it ... | 09/18/2007 |
| 7259431 | Static random access memory using thin film transistors A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent ... | 08/21/2007 |
| 7238990 | Interlayer dielectric under stress for an integrated circuit An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-co... | 07/03/2007 |
| 7221031 | Semiconductor device having sufficient process margin and method of forming same According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first p... | 05/22/2007 |
| 7217978 | SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concern... | 05/15/2007 |
| 7214990 | Memory cell with reduced soft error rate The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transi... | 05/08/2007 |
| 7208369 | Dual poly layer and method of manufacture Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method al... | 04/24/2007 |
| 7206218 | Stable memory cell with improved operation speed A memory cell, including a word line, a bit line, a first node storing a bit value voltage level, a driver transistor coupled between the first node and a ground level, and at least one data transfer transistor having a gate electrode coupled to the word line, a sou... | 04/17/2007 |
| 7199428 | Master chip, semiconductor memory, and method for manufacturing semiconductor memory A semiconductor memory includes first to sixth ridges, an insulating layers on the first to sixth ridges, a first gate line above the first to fourth ridges, and a second gate line above the third to sixth ridges, wherein the first and sixth ridges, the insulating l... | 04/03/2007 |
| 7196424 | Semiconductor device A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor c... | 03/27/2007 |
| 7187036 | Connection structure for SOI devices A semiconductor contact connection structure and the method for forming the same are disclosed. The connection structure has a first semiconductor device formed on an insulator substrate. A non-conducting gate interconnect layer is formed on the insulator substrate ... | 03/06/2007 |
| 7180126 | Multi-level memory cell array with lateral floating spacers An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed... | 02/20/2007 |
| 7166896 | Cross diffusion barrier layer in polysilicon A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of sec... | 01/23/2007 |
| 7161845 | Static random access memory device having a memory cell with multiple bit-elements A memory cell for a static random access memory (SRAM) is disclosed that can be programmed to have a one-bit cell or a multi-bit cell (i.e, including two or more latches) according to a desired amount of cell current. For lower current needs, the memory cell can inc... | 01/09/2007 |
| 7157763 | SRAM cell structure and manufacturing method thereof A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an openi... | 01/02/2007 |
| 7145194 | Semiconductor integrated circuit device and a method of manufacturing the same In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size, in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TiN f... | 12/05/2006 |
| 7138312 | Semiconductor device and method for fabricating the same The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed nea... | 11/21/2006 |
| 7105900 | Reduced floating body effect static random access memory cells and methods for fabricating the same An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a bod... | 09/12/2006 |
| 7099182 | Static random access memory and pseudo-static noise margin measuring method A first inverter includes a first load element and a first transistor, which are connected between first and second terminals in series, a first input terminal and a first output terminal. A second inverter includes a second load element and a second transistor, whi... | 08/29/2006 |
