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...During the Civil War, the Confederacy established its own Patent Office which issued 266 patents, a third of which concerned implements of war.
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| Number | Title | Issue Date |
| 7439126 | Method for manufacturing semiconductor memory A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, comprises a step of forming a polysilicon plug having a large-diameter portion on a side of the capacitor, a step of forming a hole reaching the large-diamet... | 10/21/2008 |
| 7429507 | Semiconductor device having both memory and logic circuit and its manufacture A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the s... | 09/30/2008 |
| 7402864 | Method for forming a DRAM semiconductor device with a sense amplifier A method for forming a sense amplifier of a semiconductor device prevents bit lines from being bridged to each other by a stepped portion created on an insulation interlayer due to irregular density of a P-type impurity, which is ion-implanted into an insulation int... | 07/22/2008 |
| 7381613 | Self-aligned MIM capacitor process for embedded DRAM A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive materia... | 06/03/2008 |
| 7358575 | Method of fabricating SRAM device A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on... | 04/15/2008 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7265051 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are... | 09/04/2007 |
| 7151303 | Fully-depleted (FD) (SOI) MOSFET access transistor A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. ... | 12/19/2006 |
| 7126154 | Test structure for a single-sided buried strap DRAM memory cell array A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory ce... | 10/24/2006 |
| 6703673 | SOI DRAM having P-doped poly gate for a memory pass transistor An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substa... | 03/09/2004 |
| 6703306 | Methods of fabricating integrated circuit memories including titanium nitride bit lines Integrated circuit memory devices include a memory cell field effect transistor in an integrated circuit substrate, a conductive plug that electrically contacts the memory cell field effect transistor and a titanium nitride bit line that electrically cont... | 03/09/2004 |
| 6700169 | Semiconductor memory device A semiconductor memory device of the present invention having sense amplifier transistors connected to complementary bit lines of a memory cell array and sense amplifier driver transistors driving the sense amplifier transistors, wherein the sense amplifi... | 03/02/2004 |
| 6700821 | Programmable mosfet technology and programmable address decode and correction Structures and methods for PLA capability on a DRAM chip according to a DRAM optimized process flow are provided by the present invention. These structures and methods include using MOSFET devices as re-programmable elements in memory address decode circu... | 03/02/2004 |
| 6696351 | Semiconductor device having a selectively deposited conductive layer A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circu... | 02/24/2004 |
| 6696762 | Bi-level digit line architecture for high density DRAMS There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie ... | 02/24/2004 |
| 6693834 | Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line conta... | 02/17/2004 |
| 6690053 | Shared contact in a semiconductor device in which DRAMs and SRAMs are combined and method of manufacturing the same The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11... | 02/10/2004 |
| 6687148 | High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capabili... | 02/03/2004 |
| 6687177 | Reference cells with integration capacitor A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint voltage via equalisation between the dummy memory cell havin... | 02/03/2004 |
| 6678194 | Sense amplifier arrangement for semiconductor memory device A semiconductor memory device including a plurality of cell arrays (121 to 128) and a plurality of sense amplifier sections is disclosed. Adjacent cell arrays may have a sense amplifier section disposed between. Sense amplifiers (131 to 163) within a sens... | 01/13/2004 |
| 6674678 | Sense amplifier control circuit of semiconductor memory device A sense amplifier section of a semiconductor memory device includes a memory cell array and a plurality of bit line pairs arranged in a column direction of the memory cell array. The sense amplifier section is configured to control the transfer of data to... | 01/06/2004 |
| 6674112 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a semiconductor substrate and operates when supplied with appositive supply voltage and a circuit ground potential. The device has word lines, pairs of bit lines, data storage capacitors, and N-channel MOSFETs... | 01/06/2004 |
| 6670667 | Asymmetric gates for high density DRAM A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment... | 12/30/2003 |
| 6671198 | Semiconductor device When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between... | 12/30/2003 |
| 6670665 | Memory module with improved electrical properties A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. F... | 12/30/2003 |
| 6670663 | DRAM cell capacitor and manufacturing method thereof A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact b... | 12/30/2003 |
| 6667503 | Semiconductor trench capacitor Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. Th... | 12/23/2003 |
| 6664806 | Memory address and decode circuits with ultra thin body transistors A decoder for a memory device is provided. The decoder array includes a number of address lines and a number of output lines. The address lines and the output lines form an array. The decoder includes a number of vertical pillars extending outwardly from ... | 12/16/2003 |
| 6657248 | Semiconductor device having groove isolation structure and gate oxide films with different thickness There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallo... | 12/02/2003 |
| 6656781 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, HAVING FIRST AND SECOND SEMICONDUCTOR REGIONS WITH FIELD SHIELD ISOLATION STRUCTURES AND A FIELD OXIDE FILM COVERING A JUNCTION BETWEEN SEMICONDUCTOR REGIONS A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover th... | 12/02/2003 |
| 6653690 | Semiconductor device comprising high density integrated circuit having a large number of insulated gate field effect transistors It is a purpose of the invention to provide a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors having minute size and improved performance and uniformity. The source contact... | 11/25/2003 |
| 6649984 | Logic-merged memory In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory o... | 11/18/2003 |
| 6646907 | Semiconductor memory device A semiconductor memory device uses memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability. A semiconductor memory device includes memory cells formed on a main surface of a ... | 11/11/2003 |
| 6645845 | Methods of forming interconnect regions of integrated circuitry In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier lay... | 11/11/2003 |
| 6643160 | Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements A data bus architecture for integrated circuit embedded dynamic random access memory having a large aspect ratio serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. The me... | 11/04/2003 |
| 6639822 | Dynamic ram-and semiconductor device There are provided a plurality of memory mats, including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells coupled to the plurality of bit lines, and the plurality of word lines are provided in a direction of the bit lin... | 10/28/2003 |
| 6639863 | Semiconductor integrated circuit device having link element A semiconductor integrated circuit device has a first LT fuse group for storing replacement information used in a memory array; a second LT fuse group for storing confirmation information to confirm whether the first LT fuse group has accurately stored th... | 10/28/2003 |
| 6635915 | Semiconductor device having trench capacitor formed in SOI substrate A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor ... | 10/21/2003 |
| 6635515 | Method of manufacturing a semiconductor device having signal line above main ground or main VDD line A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic eva... | 10/21/2003 |
| 6635526 | Structure and method for dual work function logic devices in vertical DRAM process Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the su... | 10/21/2003 |
