Class 257/E27.096 - Vertical transistor (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 197
Last issue date: 09/02/2008

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Number	Title	Issue Date
7420230	MOSFET-type semiconductor device, and method of manufacturing the same A MOSFET-type semiconductor device includes a monocrystalline semiconductor layer formed in a shape of a thin wall on a insulating film, a gate electrode straddling over the semiconductor layer around the middle portion of the wall-shaped semiconductor layer via a g...	09/02/2008
7391070	Semiconductor structures and memory device constructions The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and ...	06/24/2008
7368778	DRAM having at least three layered impurity regions between channel holes and method of fabricating same Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate...	05/06/2008
7364997	Methods of forming integrated circuitry and methods of forming local interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive material in a second circuitry area. The field oxide is etched from the first circuitry area. After the et...	04/29/2008
7312493	Semiconductor device and method of manufacturing the same A semiconductor device having a vertical gate and method of manufacturing the same are disclosed. An example semiconductor device includes a pair of first source/drain regions formed apart from each other by a predetermined distance on a silicon substrate, a first s...	12/25/2007
7276754	Annular gate and technique for fabricating an annular gate A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surfac...	10/02/2007
7247905	Offset vertical device The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor...	07/24/2007
7193268	Semiconductor device In a semiconductor device in which gate trenches and source trenches are formed, when the semiconductor device is flatly viewed, N+ type source areas are formed in parallel with the gate trenches to ease the miniaturization of the semiconductor device. P	03/20/2007
6700826	Semiconductor apparatus A simply structured, and highly reliable semiconductor apparatus having a large storage capacity. The apparatus has a plurality of memory cells on one semiconductor substrate, each including a capacitor having first and second electrodes, and a switching ...	03/02/2004
6680501	Semiconductor device A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line...	01/20/2004
6680864	Method for reading a vertical gain cell and array for a dynamic random access memory A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body por...	01/20/2004
6660581	Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devices Form a bitline contact to deep trench gates separated from a substrate body by gate oxide with sources next to the gates near the top of the body and drains formed in the body of the substrate connected to a deep trench capacitor, with sidewall spacers be...	12/09/2003
6638812	Method for producing a memory cell for a semiconductor memory The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole, includes the steps of forming the memory node in the monocrystalline silicon of the substrate...	10/28/2003
6638815	Formation of self-aligned vertical connector In a vertical-transistor based semiconductor structure, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a sacrificial insulato...	10/28/2003
6635526	Structure and method for dual work function logic devices in vertical DRAM process Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the su...	10/21/2003
6630379	Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pitch A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor...	10/07/2003
6620699	Method for forming inside nitride spacer for deep trench device DRAM cell A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide lay...	09/16/2003
6620677	Support liner for isolation trench height control in vertical DRAM processing A method of manufacturing a vertical DRAM device (10) having isolation trenches (38) with a controlled height. A support liner (54) is disposed over support regions (18) of a wafer. A first insulating layer is disposed over the wafer, and the first insula...	09/16/2003
6586795	DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties Memory cells each include one transistor and one capacitor. A memory node of the capacitor is disposed in a first indentation, while a gate electrode of the transistor is disposed in a second indentation. An upper source/drain region, a channel region, an...	07/01/2003
6566187	DRAM cell system and method for producing same DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a peripher...	05/20/2003
6552382	Scalable vertical DRAM cell structure and its manufacturing methods A scalable vertical DRAM cell structure comprising a scalable trench region and a self-aligned common-drain diffusion region are disclosed by the present invention, in which the scalable trench region comprises a deep-trench region having a vertical trans...	04/22/2003
6537871	Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor A memory cell. The memory cell includes an access transistor. The access transistor is formed in a pillar of single crystal semiconductor material. The transistor has first and second source/drain regions and a body region that are vertically aligned. The...	03/25/2003
6534824	Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gat...	03/18/2003
6501117	Static self-refreshing DRAM structure and operating mode A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first d...	12/31/2002
6496401	Memory cell configuration A memory cell configuration has memory cells, each with a trench capacitor in a trench and a vertical transistor, which is used as a selection transistor. The trench capacitors in adjacent memory cells are arranged next to a bit line and are connected to ...	12/17/2002
6492233	Memory cell with vertical transistor and buried word and body lines An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit Vertically oriented access transistors are formed on semiconductor pillars on buried bit lin...	12/10/2002
6492221	DRAM cell arrangement A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memo...	12/10/2002
6469335	Semiconductor memory having a memory cell array A semiconductor memory such as, for example, a DRAM (Dynamic Random Access Memory) includes a memory cell array and an addressing periphery. A first memory cell having a first selection transistor and a first storage capacitor, and a second memory cell ha...	10/22/2002
6452224	Method for manufacture of improved deep trench eDRAM capacitor and structure produced thereby A capacitor is formed in a trench in a well/substrate doped with a first polarity. A dielectric isolation collar formed on trench sidewalls is recessed below the trench top and is spaced from the trench bottom. Therebelow, a counterdoped plate electrode r...	09/17/2002
6448610	Memory cell with trench, and method for production thereof The invention relates to a memory cell that has a trench. A trench capacitor is configured in the trench. In addition, a vertical transistor is formed in the trench, above the trench capacitor. To connect the gate material of the vertical transistor to a ...	09/10/2002
6440801	Structure for folded architecture pillar memory cell A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the oth...	08/27/2002
6437388	Compact trench capacitor memory cell with body contact A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical ...	08/20/2002
6420228	Method for the production of a DRAM cell configuration A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a stor...	07/16/2002
6420751	Semiconductor device and method of manufacturing the same A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. T...	07/16/2002
6383860	Semiconductor device and method of manufacturing the same A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a stora...	05/07/2002
6339239	DRAM cell layout for node capacitance enhancement A layout pattern for increasing the spacing between the deep trenches of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact to bitlines arranged...	01/15/2002
6339241	Structure and process for 6F2 trench capacitor DRAM cell with vertical MOSFET and 3F bitline pitch A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor...	01/15/2002
6335239	Manufacturing a DRAM cell having an annular signal transfer region A memory device formed in a substrate having a trench with side walls formed in the substrate. The device includes a bit line conductor and a word line conductor. A signal storage node has a first electrode, a second electrode formed within the trench, an...	01/01/2002
6303425	Semiconductor device and method of manufacturing the same A first impurity diffusion layer forms one of source/drain regions and also forms a bit line. A first semiconductor layer, a channel semiconductor layer and a second semiconductor layer, which forms the other of source/drain regions and also forms a stora...	10/16/2001
6282116	Dynamic random access memory A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active a...	08/28/2001

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Class 257/E27.096 - Vertical transistor (EPO)