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| Number | Title | Issue Date |
| 7439568 | Vertical body-contacted SOI transistor A vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate i... | 10/21/2008 |
| 7436069 | Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A ... | 10/14/2008 |
| 7391070 | Semiconductor structures and memory device constructions The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and ... | 06/24/2008 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 07/03/2007 |
| 7195973 | Method for fabricating a trench capacitor with an insulation collar and corresponding trench capacitor The present invention provides a method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar select... | 03/27/2007 |
| 7193262 | Low-cost deep trench decoupling capacitor device and process of manufacture A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design. ... | 03/20/2007 |
| 7157766 | Variable capactor structure and method of manufacture A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped... | 01/02/2007 |
| 7115938 | Non-volatile memory cell and method of forming the same A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switchi... | 10/03/2006 |
| 7091541 | Semiconductor device using a conductive film and method of manufacturing the same A semiconductor device has a capacitive element including a first conductive film formed on the bottom and wall surfaces of an opening formed in an insulating film on a substrate, a dielectric film formed on the first conductive film, and a second conductive film fo... | 08/15/2006 |
| 6873000 | Storage cell field and method of producing the same A storage cell field has a plurality of storage cells formed in a substrate of a first doping type, said storage cells comprising a trench capacitor arranged in said substrate and a selection transistor associated with said trench capacitor and provided with a trans... | 03/29/2005 |
| 6689656 | Dynamic random access memory and the method for fabricating thereof The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interpos... | 02/10/2004 |
| 6664167 | Memory with trench capacitor and selection transistor and method for fabricating it A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least ... | 12/16/2003 |
| 6590249 | One-transistor memory cell configuration and method for its fabrication In a method for fabricating a dynamic memory cell in a semiconductor substrate having a trench capacitor 1 and a selection transistor 2 and a semiconductor memory having such a memory cell, a dielectric insulator layer 17, 201 is formed between the select... | 07/08/2003 |
| 6590248 | Dynamic random access memory and the method for fabricating thereof The present invention discloses a dynamic random access memory and the method for fabricating thereof. A first silicon substrate having a trench capacitor and a second silicon substrate having a transistor are formed with a double layer, which is interpos... | 07/08/2003 |
| 6552378 | Ultra compact DRAM cell and method of making A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transf... | 04/22/2003 |
| 6534811 | DRAM cell with high integration density A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on... | 03/18/2003 |
| 6399435 | Method for producing a DRAM cell with a trench capacitor The present invention provides a method for fabricating a DRAM cell having a trench capacitor. In order to simplify the fabrication method for a DRAM cell, to ensure a high yield and to achieve a high packing density of the DRAM cells, the invention propo... | 06/04/2002 |
| 6373085 | Semiconductor memory cell having two epitaxial layers and its manufacturing method A memory cell incorporated in a dynamic RAM is disclosed. The memory cell comprises a capacitor having a storage electrode formed in a trench, a first semiconductor layer formed on the capacitor, a connection member formed in the hole, a second semiconduc... | 04/16/2002 |
| 6326262 | Method for fabricating epitaxy layer A method of fabricating an epitaxial layer includes providing a substrate having a substrate surface with an at least partly uncovered monocrytalline region, and at least one electrically insulating region adjoining the monocrystalline region and being at... | 12/04/2001 |
| 6236079 | Dynamic semiconductor memory device having a trench capacitor A semiconductor memory device includes a semiconductor substrate and first, second, third and fourth spaced apart word lines formed on the semiconductor substrate and extending in a first direction. First, second, and third spaced apart bit lines are form... | 05/22/2001 |
| 6218693 | Dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor by a novel fabrication method An improved dynamic random access memory (DRAM) cell using a novel buried horizontal trench capacitor was achieved. A capacitor trench is etched in a silicon substrate. A first high-k dielectric layer is formed on the trench surface, and the trench is fil... | 04/17/2001 |
| 6191442 | DRAM memory with TFT superposed on a trench capacitor In order to correspond to high integration with large capacity of a semiconductor device, provided are a structure of the semiconductor device and a method for manufacturing the same in which a horizontal dimension can be reduced in either a memory cell r... | 02/20/2001 |
| 6180973 | Semiconductor memory device and method for manufacturing the same A semiconductor memory device includes a semiconductor substrate, an element isolation film formed on the substrate, element formation regions each defined in an island form in the surface of the substrate by the element isolation film, trenches formed in... | 01/30/2001 |
| 6180975 | Depletion strap semiconductor memory device A memory cell structure which uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor is described. The buried strap connection between the trench capacitor and the bitline con... | 01/30/2001 |
| 6171923 | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer ... | 01/09/2001 |
| 6153474 | Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.... | 11/28/2000 |
| 6069819 | Variable threshold voltage DRAM cell A memory cell is provided that includes a transistor and a capacitor. The transistor has a gate, a drain, a source, and a back-plane gate, and the capacitor has first and second electrodes. The back-plane gate of the transistor is connected to the first e... | 05/30/2000 |
| 6037620 | DRAM cell with transfer device extending along perimeter of trench storage capacitor A structure and method of manufacture is disclosed herein for a semiconductor memory cell having size of 4.5 F2 or less, where F is the minimum lithographic dimension. The semiconductor memory cell includes a storage capacitor formed in a trench, a transf... | 03/14/2000 |
| 6037210 | Memory cell with transfer device node in selective polysilicon A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal ... | 03/14/2000 |
| 6015985 | Deep trench with enhanced sidewall surface area The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.... | 01/18/2000 |
| 6004844 | Unit cell layout and transfer gate design for high density DRAMs A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the t... | 12/21/1999 |
| 5990511 | Memory cell with transfer device node in selective polysilicon A memory cell is constructed with one electrode of the transfer device extending over a trench capacitor, saving about 6.5% of cell area. Selective polysilicon for a strap seeded from the trench is grown in the same step in which selective single crystal ... | 11/23/1999 |
| 5976945 | Method for fabricating a DRAM cell structure on an SOI wafer incorporating a two dimensional trench capacitor A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer ... | 11/02/1999 |
| 5945703 | Semiconductor memory device and manufacturing method therefor In a semiconductor memory device, a capacitor with a trench having a laterally expanded bottom part is provided, the area above the laterally expanded part being provided for a transistor and cell separation, this resulting in an increase in the degree of... | 08/31/1999 |
| 5943581 | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits An improved DRAM cell using a novel buried reservoir capacitor is achieved. The method forms an array of N+ doped regions in a substrate. P-wells are formed in an epitaxy layer on the substrate. A field oxide (FOX) is formed surrounding the de... | 08/24/1999 |
| 5942778 | Switching transistor and capacitor for memory cell A semiconductor device includes (a) a first conductivity type semiconductor substrate having a plurality of trenches formed therein, the trenches defining a plurality of device regions between adjacent trenches, (b) a second conductivity type diffusion la... | 08/24/1999 |
| 5936271 | Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers A DRAM unit cell is disclosed which comprises a trench capacitor having a signal electrode, a bit line, a planar active word line overlapping the trench capacitor and a planar FET having a main conducting path coupled between the signal electrode of the t... | 08/10/1999 |
| 5930107 | Dual trench capacitor A dual trench structure for a high density trench DRAM. The dual trench structure, each of which can reside in part under the access device of a respective cell, does not require the use of expensive selective epi growth techniques. A sub-minimum lithogra... | 07/27/1999 |
| 5920777 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode correspondin... | 07/06/1999 |
| 5893735 | Three-dimensional device layout with sub-groundrule features Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base ... | 04/13/1999 |
