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| Number | Title | Issue Date |
| 7442976 | DRAM cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the s... | 10/28/2008 |
| 7425499 | Methods for forming interconnects in vias and microelectronic workpieces including such interconnects Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinnin... | 09/16/2008 |
| 7375016 | Method for fabricating semiconductor device Disclosed herein is a method for fabricating a memory device. According to the present invention, during an etching process for forming a recess gate region, a device isolation film is etched using a mask partially exposing a channel region and its neighboring devic... | 05/20/2008 |
| 7372088 | Vertical gate semiconductor device and method for fabricating the same A source region is formed by performing ion implantation plural times to diffuse an impurity from the upper surface of a semiconductor region toward a region far dawn therefrom and to increase impurity concentration in the vicinity of the upper surface of the semico... | 05/13/2008 |
| 7332771 | Trench-gate semiconductor devices A trench-gate vertical power transistor in which the trench-gates (11) are parallel stripes which extend across the active area (100). Source regions (13) and ruggedness regions (15) extend to a source contact surface as alternating strip... | 02/19/2008 |
| 7279743 | Closed cell trench metal-oxide-semiconductor field effect transistor Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body regi... | 10/09/2007 |
| 7259424 | Semiconductor device having a trench with a step-free insulation film A method of manufacturing a semiconductor device provided with a MOS field effect transistor having a channel region of a first conduction type formed in a surface layer portion of a semiconductor substrate, a source region of a second conduction type formed on a ri... | 08/21/2007 |
| 7250336 | Method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the t... | 07/31/2007 |
| 7242058 | Lateral semiconductor device using trench structure and method of manufacturing the same A semiconductor device has a semiconductor substrate and a trench region having at least one trench disposed on a surface of the semiconductor substrate and having a trench length, a trench width and a trench depth. A well region is disposed in the substrate and sur... | 07/10/2007 |
| 7227226 | Semiconductor device with buried-oxide film The present invention is a semiconductor device which includes: a semiconductor substrate; a BOX film disposed on top of the semiconductor substrate; an active layer disposed on top of the BOX film; a base region disposed proximate to a surface of the active layer; ... | 06/05/2007 |
| 7220634 | NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing... | 05/22/2007 |
| 7199416 | Systems and methods for a memory and/or selection element formed within a recess in a metal line The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various e... | 04/03/2007 |
| 7193270 | Semiconductor device with a vertical transistor A semiconductor device which, even when a vertical transistor is adopted, is able to prevent a product yield from decreasing and performance from deteriorating, and at the same time, to achieve high-density integration of chips and high performance. The semiconducto... | 03/20/2007 |
| 7190020 | Non-planar flash memory having shielding between floating gates A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in the same column. The second plurality of memory cells is coupled to the first plurality of memory cells ... | 03/13/2007 |
| 7180115 | DRAM cell structure with tunnel barrier The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode... | 02/20/2007 |
| 7176078 | Nonvolatile semiconductor memory device having strap region and fabricating method thereof In a nonvolatile semiconductor memory device having a memory cell array region and a strap region for providing voltage to the memory cell array region, in the memory cell array region, a plurality of word lines and a plurality of source lines are formed in a row di... | 02/13/2007 |
| 7129130 | Out of the box vertical transistor for eDRAM on SOI The present invention provides a vertical memory device formed in a silicon-on-insulator substrate, where a bitline contacting the upper surface of the silicon-on-insulator substrate is electrically connected to the vertical memory device through an upper strap diff... | 10/31/2006 |
| 6995437 | Semiconductor device with core and periphery regions A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A fi... | 02/07/2006 |
| 6689660 | 4 F2 folded bit line DRAM cell structure having buried bit and word lines A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonal... | 02/10/2004 |
| 6656807 | Grooved planar DRAM transfer device using buried pocket A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion incl... | 12/02/2003 |
| 6627940 | Memory cell arrangement A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in ... | 09/30/2003 |
| 6617651 | Semiconductor memory device A semiconductor memory device has full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semicon... | 09/09/2003 |
| 6614074 | Grooved planar DRAM transfer device using buried pocket A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion incl... | 09/02/2003 |
| 6603168 | Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method An integrated circuit memory device includes a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar comprising a lower source/drain region for a cell access trans... | 08/05/2003 |
| 6593614 | Integrated circuit configuration having at least one transistor and one capacitor, and method for fabricating it A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive... | 07/15/2003 |
| 6573545 | Semiconductor memory device for eliminating floating body effect and method of fabricating the same A semiconductor memory device from which a floating body effect is eliminated and which has enhanced immunity to external noise, and a method of fabricating the same are provided. The memory device includes a semiconductor substrate. A plurality of bit li... | 06/03/2003 |
| 6566182 | DRAM memory cell for DRAM memory device and method for manufacturing it A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction betw... | 05/20/2003 |
| 6563155 | Cross point type DRAM cell composed of a pillar having an active region A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit li... | 05/13/2003 |
| 6559491 | Folded bit line DRAM with ultra thin body transistors A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single... | 05/06/2003 |
| 6531727 | Open bit line DRAM with ultra thin body transistors Structures and method for an open bit line DRAM device are provided. The open bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. The p... | 03/11/2003 |
| 6504200 | DRAM cell configuration and fabrication method Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are v... | 01/07/2003 |
| 6498062 | DRAM access transistor A method of forming memory devices, such as DRAM access transistors, having recessed gate structures is disclose. Field oxide areas for isolation are first formed over a semiconductor substrate subsequent to which transistor grooves are patterned and etch... | 12/24/2002 |
| 6476434 | 4 F2 folded bit line dram cell structure having buried bit and word lines A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonal... | 11/05/2002 |
| 6468887 | Semiconductor device and a method of manufacturing the same In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. ... | 10/22/2002 |
| 6465299 | Semiconductor memory and method for fabricating the same Semiconductor memory and method for fabricating the same, the semiconductor memory including a cell transistor having a trench region formed in a semiconductor substrate and channel regions at sides of the trench region, source/drain regions formed in a b... | 10/15/2002 |
| 6455886 | Structure and process for compact cell area in a stacked capacitor cell array A method for forming, and a structure for a semiconductor device having vertically-oriented transistors connected to stacked capacitor cells, wherein a contact area for the capacitors enables a compact cell. A vertically-oriented transistor is formed in a... | 09/24/2002 |
| 6440801 | Structure for folded architecture pillar memory cell A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the oth... | 08/27/2002 |
| 6420751 | Semiconductor device and method of manufacturing the same A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. T... | 07/16/2002 |
| 6399435 | Method for producing a DRAM cell with a trench capacitor The present invention provides a method for fabricating a DRAM cell having a trench capacitor. In order to simplify the fabrication method for a DRAM cell, to ensure a high yield and to achieve a high packing density of the DRAM cells, the invention propo... | 06/04/2002 |
| 6380027 | Dual tox trench dram structures and process using V-groove A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first... | 04/30/2002 |
