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| Number | Title | Issue Date |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7235838 | Semiconductor device substrate with embedded capacitor A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a ... | 06/26/2007 |
| 7202518 | Integrated dynamic random access memory element, array and process for fabricating such elements An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend betwee... | 04/10/2007 |
| 7126177 | Semiconductor memory device, semiconductor device, and method for production thereof Disclosed are a semiconductor memory device, a semiconductor device, and a method for production thereof. The semiconductor memory device and semiconductor device do not need for a distance for alignment of lithography to make the contact hole with lithography to fo... | 10/24/2006 |
| 6639243 | DRAM cell constructions The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to ... | 10/28/2003 |
| 6617651 | Semiconductor memory device A semiconductor memory device has full depletion type MISFETs to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semicon... | 09/09/2003 |
| 6569734 | Method for two-sided fabrication of a memory array A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, op... | 05/27/2003 |
| 6569733 | Gate device with raised channel and method A method of forming a gate device which includes an elongated projection on a substrate. The elongated projection protrudes from a surrounding area of the substrate and includes an access channel for the gate device. A first terminal and a second terminal... | 05/27/2003 |
| 6566182 | DRAM memory cell for DRAM memory device and method for manufacturing it A DRAM memory cell includes a MOSFET selection transistor having a drain region and a source region in a semiconductor substrate column. A current channel, which is capable of being actuated by a control gate electrode extends in a vertical direction betw... | 05/20/2003 |
| 6472703 | Semiconductor memory device and method for fabricating the same A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffus... | 10/29/2002 |
| 6458638 | Method for fabricating a semiconductor memory device having silicon-on-insulator (SOI) structure A method for fabricating a SOI semiconductor device including providing a semiconductor substrate; forming a device isolation layer in and on a first surface of the semiconductor substrate to define an active region, including a source/drain region, and a... | 10/01/2002 |
| 6330181 | Method of forming a gate device with raised channel A method for fabricating a gate device includes forming an elongated projection (422) on a substrate (412). The elongated projection (422) protrudes from a surrounding area (424) of the substrate (412) and includes an access channel (434) for the gate dev... | 12/11/2001 |
| 6329239 | Dram cell formed on an insulating layer having a vertical channel and a manufacturing method thereof A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel. The each memory cell includes a first junction region surro... | 12/11/2001 |
| 6306719 | Method for manufacturing a semiconductor device A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a capacit... | 10/23/2001 |
| 6297090 | Method for fabricating a high-density semiconductor memory device A method for fabricating a high-density semiconductor memory device which can reduce chip size and increase memory device characteristics. The present invention provides SOI type memory device. The capacitor is embedded in the insulator below the semicond... | 10/02/2001 |
| 6294806 | Semiconductor memory device having silicon-on-insulator (SOI) structure and method for fabricating thereof A SOI semiconductor device including a substrate, a first gate electrode formed on a first surface of the substrate between a source/drain region, a first insulating layer formed on the first gate electrode and the first surface of the substrate, a capaci... | 09/25/2001 |
| 6242298 | Semiconductor memory device having epitaxial planar capacitor and method for manufacturing the same A semiconductor memory device includes a memory cell constructed from an epitaxial planar capacitor and a switching transistor. The epitaxial planar capacitor includes a first and a second electrode layers and a dielectric thin film composed of ferroelect... | 06/05/2001 |
| 6211531 | Controllable conduction device A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer... | 04/03/2001 |
| 6169308 | Semiconductor memory device and manufacturing method thereof A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhi... | 01/02/2001 |
| 6077740 | Method for forming a semiconductor device contact structure comprising a contour A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and ... | 06/20/2000 |
| 6072208 | Dynamic random access memory fabricated with SOI substrate In a dynamic random access memory (DRAM), a step produced by forming a stacked capacitor can be prevented from being produced and increased, thereby facilitating the patterning of an upper layer (wiring, etc.). Further, the pattern layout can be made with... | 06/06/2000 |
| 6060723 | Controllable conduction device A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer... | 05/09/2000 |
| 6015990 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device comprises a matrix of memory cells, each having a transistor and a capacitor. A first electrode, a dielectric film and a second electrode are sequentially staked on a silicon monocrystalline substrate and epitaxially grown to... | 01/18/2000 |
| 5968840 | Dynamic random access memory using silicon-on-insulator techniques The present invention discloses a method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate and recessing just the cell area where a memory dev... | 10/19/1999 |
| 5959322 | Isolated SOI memory structure with vertically formed transistor and storage capacitor in a substrate A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a compaci... | 09/28/1999 |
| 5956586 | Semiconductor memory device and method of manufacturing the same A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bi... | 09/21/1999 |
| 5939745 | Dynamic access memory using silicon-on-insulator The present invention discloses a method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate and recessing just the cell area where a memory dev... | 08/17/1999 |
| 5892256 | Semiconductor memory and a method of manufacturing the same A semiconductor memory having storage cells each consisting of a MIS transistor and a capacitor, and a method of manufacturing the same. The semiconductor memory comprises a semiconductor substrate, an insulating layer formed on the semiconductor substrat... | 04/06/1999 |
| 5888864 | Manufacturing method of DRAM Cell formed on an insulating layer having a vertical channel A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel. The each memory cell includes a first junction region surro... | 03/30/1999 |
| 5776789 | Method for fabricating a semiconductor memory device A semiconductor memory device comprises a silicon layer having a first diffused region and a second diffused region formed therein, a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffus... | 07/07/1998 |
| 5719418 | Contact-substrate for a semiconductor device comprising a contour A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and ... | 02/17/1998 |
| 5684316 | Semiconductor memory device provided with capacitors formed above and below a cell transistor A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, an... | 11/04/1997 |
| 5661063 | Semiconductor memory device provided with capacitors formed above and below a cell transistor and method for manufacturing the same A semiconductor memory device provided with capacitors formed above and below a cell transistor includes first and second transistors formed in a first level, a first storage electrode connected to the first transistor and formed below the first level, an... | 08/26/1997 |
| 5650957 | Semiconductor memory cell and process for formation thereof A semiconductor memory cell and a process for formation thereof is disclosed. A capacitor is disposed below a transistor, so that a DRAM cell that may be suitable for a high density semiconductor device is produced. A semiconductor device according to the... | 07/22/1997 |
| 5631186 | Method for making a dynamic random access memory using silicon-on-insulator techniques The present invention discloses a method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate and recessing just the cell area where a memory dev... | 05/20/1997 |
| 5608248 | Semiconductor memory device with planarization structure A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bi... | 03/04/1997 |
| 5523254 | Method for production of SOI transistor device and SOI transistor A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two... | 06/04/1996 |
| 5506163 | Method of making a semiconductor device In a method of manufacturing a DRAM by using a laminate SOI technique, which makes it possible to form a thin semiconductor film of a uniform thickness, the method includes steps of forming a step portion on a major surface of a silicon substrate, forming... | 04/09/1996 |
| 5492853 | Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and ... | 02/20/1996 |
| 5493137 | Method for production of SOI transistor device and SOI transistor device A wafer bonding method for forming a SOI structure comprising the steps of bringing wafers into proximity in a state with one wafer a slight, substantially uniform clearance away from the other wafer and pressing one point of at least one wafer of the two... | 02/20/1996 |
