Class 257/E27.087 - With bit line higher than capacitor (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 35
Last issue date: 06/03/2008

Number	Title	Issue Date
7381613	Self-aligned MIM capacitor process for embedded DRAM A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive materia...	06/03/2008
7345333	Double sided container process used during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is prov...	03/18/2008
7304341	Semiconductor device and method for fabricating the same A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess an...	12/04/2007
7202519	Memory cells having an access transistor with a source/drain region coupled to a capacitor through an extension Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells furt...	04/10/2007
7151291	Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first la...	12/19/2006
7145193	Semiconductor integrated circuit device and process for manufacturing the same In a peripheral circuit region of a DRAM, two connection holes, for connecting a first layer line and a second layer line electrically are opened separately in two processes. After forming the connection holes, plugs are formed in the respective connection holes.	12/05/2006
6703656	Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12" wafer Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved f...	03/09/2004
6696336	Double sided container process used during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric la...	02/24/2004
6693319	Container capacitor structure and method of formation thereof Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess betwee...	02/17/2004
6690055	Devices containing platinum-rhodium layers and methods A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula Ly RhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and elec...	02/10/2004
6690053	Shared contact in a semiconductor device in which DRAMs and SRAMs are combined and method of manufacturing the same The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11...	02/10/2004
6677636	Structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line conta...	01/13/2004
6674111	Semiconductor device having a logic transistor therein An etch stopper member is formed under a cell plate electrode so as to surround an active region along a periphery of the cell plate electrode. The etch stopper member is formed from a material that is resistant to an etchant of a first interlayer insulat...	01/06/2004
6670238	Method and structure for reducing contact aspect ratios An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line conta...	12/30/2003
6664159	Mixed metal nitride and boride barrier layers Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of Mx Aly Nz Bw alloy diffus...	12/16/2003
6660610	Devices having improved capacitance and methods of their fabrication A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has first and second conductive plates and a dielectric is formed from the first conductive plate...	12/09/2003
6661051	Container capacitor structure and method of formation thereof Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode ("bottom electrodes") of the container capacitor structure. The etch provides a recess betwee...	12/09/2003
6656835	Process for low temperature atomic layer deposition of Rh A method for the formation of rhodium films with good step coverage is disclosed. Rhodium films are formed by a low temperature atomic layer deposition technique using a first gas of rhodium group metal precursor followed by an oxygen exposure. The invent...	12/02/2003
6656801	Method of fabricating a ferroelectric stacked memory cell The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control e...	12/02/2003
6653230	Semiconductor device having concave electrode and convex electrode and method of manufacturing thereof It is intended to enable simultaneous formation of concave capacitor storage electrodes and a convex bit contact plug electrode and thereby makes it possible to reduce spaces of margins for alignment errors by decreasing the number of lithography steps. G...	11/25/2003
6649466	Method of forming DRAM circuitry In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising l...	11/18/2003
6642097	Structure for capacitor-top-plate to bit-line-contact overlay margin A novel method and structure are described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After insulating the FETs with a first insulating layer, a second insulating laye...	11/04/2003
6642093	Method for manufacturing a semiconductor device According to the present invention, a method for manufacturing a semiconductor device forms a cobalt silicide film 11 on source/drain regions 7a and 7b and a gate electrode 4 of transistors in the logic circuit region, making it possible to form a high-pe...	11/04/2003
6638801	Semiconductor device and its manufacturing method A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than...	10/28/2003
6635547	DRAM capacitor formulation using a double-sided electrode A capacitor having a double sided electrode for enhanced capacitance. In one embodiment, the double sided electrode capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The double sided electrode is preferably formed ...	10/21/2003
6627933	Method of forming minimally spaced word lines A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the t...	09/30/2003
6627493	Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (DRAM) cell structure Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within th...	09/30/2003
6624020	Fabrication method of semiconductor device with capacitor In a fabrication method of semiconductor device, a storage node connected to one of source/drain regions of an MOS (Metal Oxide Semiconductor) transistor provided at a semiconductor substrate is formed along a trench provided through a silicon nitride fil...	09/23/2003
6624461	Memory device The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and driven via word and bit lines. This memory device comprises two metallized sheets through which...	09/23/2003
6624085	Semiconductor structure, capacitor, mask and methods of manufacture thereof A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist ...	09/23/2003
6620680	Method of forming a contact structure and a container capacitor structure Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capa...	09/16/2003
6617206	Method of forming a capacitor structure A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as o...	09/09/2003
6617635	Integrated circuit devices having contact and container structures Integrated circuitry fabricated using methods for forming contact structures and container structures, as described herein, are provided. The integrated circuitry formed by the methods of the present invention, for example DRAM structures, provide capacit...	09/09/2003
6617250	Methods of depositing a layer comprising tungsten and methods of forming a transistor gate line In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising l...	09/09/2003
6238971	Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a)...	05/29/2001

PatentStorm

Bizarre Patents

PatentStorm News

Class 257/E27.087 - With bit line higher than capacitor (EPO)