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| Number | Title | Issue Date |
| 7442978 | Semiconductor memory device including multi-layer gate structure A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is forme... | 10/28/2008 |
| 7427793 | Sacrificial self-aligned interconnect structure A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and underlying a semiconductor device of a substrate assembly in order to electrically connect the active region and ... | 09/23/2008 |
| 7413950 | Methods of forming capacitors having storage electrodes including cylindrical conductive patterns A capacitor is provided including a storage node contact pad and a storage electrode. The storage electrode includes at least two cylindrical conductive patterns. The at least two cylindrical conductive patterns are electrically coupled to a portion of a surface of ... | 08/19/2008 |
| 7411241 | Vertical type nanotube semiconductor device A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate a... | 08/12/2008 |
| 7375390 | Semiconductor memory device having high electrical performance and mask and photolithography friendliness A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between ... | 05/20/2008 |
| 7372091 | Selective epitaxy vertical integrated circuit components Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are vertically oriented. These structures have regions that are doped in situ during selective epitaxial growth of t... | 05/13/2008 |
| 7368344 | Methods of reducing floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a prefe... | 05/06/2008 |
| 7368778 | DRAM having at least three layered impurity regions between channel holes and method of fabricating same Disclosed is a dynamic random access memory (DRAM) comprising a transistor having channel holes formed in the channel region thereof and cell gate structures formed in the channel holes. At least three layered impurity regions are formed in a semiconductor substrate... | 05/06/2008 |
| 7361547 | Method for forming a capacitor for use in a semiconductor device A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the ... | 04/22/2008 |
| 7355232 | Memory devices with dual-sided capacitors A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of hemispherical grained polysilicon (HSG) as part of a dual-sided lower capacitor electrode. Prior to the die... | 04/08/2008 |
| 7348623 | Semiconductor device including a MIM capacitor A semiconductor device includes: a semiconductor substrate; a first wiring formed above the semiconductor substrate with a first insulating film interposed therebetween; an MIM capacitor formed above the first insulating film; a second insulating film formed to cove... | 03/25/2008 |
| 7345333 | Double sided container process used during the manufacture of a semiconductor device A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is prov... | 03/18/2008 |
| 7332760 | Ferroelectric material for ferroelectric devices A ferroelectric material includes a superlattice structure having lead zirconate layers and barium zirconate layers such that the superlattice structure has remanent polarization exhibiting a linearly positive dependency on a driving voltage. ... | 02/19/2008 |
| 7326984 | MIS capacitor and method of formation An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a ni... | 02/05/2008 |
| 7323738 | MIS capacitor and method of formation An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to the dielectric formation, the hemispherical grained polysilicon layer may be optionally subjected to a ni... | 01/29/2008 |
| 7321144 | Semiconductor device employing buried insulating layer and method of fabricating the same A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silic... | 01/22/2008 |
| 7321146 | DRAM memory cell and method of manufacturing the same A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node cont... | 01/22/2008 |
| 7312488 | Semiconductor storage device and manufacturing method for the same There is provided a semiconductor storage device comprising a ferroelectric capacitor superior in barrier capability against penetration of hydrogen from all directions including a transverse direction. The device comprises a transistor formed on a semiconductor sub... | 12/25/2007 |
| 7304341 | Semiconductor device and method for fabricating the same A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess an... | 12/04/2007 |
| 7301192 | Dram cell pair and dram memory cell array Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two sele... | 11/27/2007 |
| 7297999 | Semiconductor device with capacitors and its manufacture method An interlayer insulating film (22) is formed on a semiconductor substrate. A conductive plug (25) is embedded in a via hole formed through the interlayer insulating film. An oxygen barrier conductive film (33) is formed on the interlayer insulat... | 11/20/2007 |
| 7294876 | FeRAM device and method for manufacturing the same An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer a... | 11/13/2007 |
| 7291879 | Semiconductor memory device including capacitor with conductive hydrogen diffusion prevention wiring film The present invention provides a semiconductor memory device which comprises an interlayer insulating film formed on a semiconductor substrate, a contact plug formed in the interlayer insulating film and having one end electrically connected to the semiconductor sub... | 11/06/2007 |
| 7288807 | Semiconductor device with capacitor element After a capacitor forming portion is formed on a semiconductor substrate by patterning an insulating film and a silicon film, a sidewall insulating film is formed on each of the side surfaces of the capacitor forming portion. Then, the insulating film is selectively... | 10/30/2007 |
| 7282756 | Structurally-stabilized capacitors and method of making of same Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechan... | 10/16/2007 |
| 7227215 | Semiconductor device having a capacitor with a stepped cylindrical structure and method of manufacturing same According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the s... | 06/05/2007 |
| 7217971 | Miniaturized semiconductor device with improved dielectric properties Diffusion layers 2–5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2–5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as... | 05/15/2007 |
| 7199419 | Memory structure for reduced floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a prefe... | 04/03/2007 |
| 7126182 | Memory circuitry The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors. Individual of the capacitors include a storage node electrode, a capacitor dielectric region, and a cell electr... | 10/24/2006 |
| 7126180 | Semiconductor device including a capacitor having improved structural stability and enhanced capacitance, and method of manufacturing the semiconductor device In a method of manufacturing a semiconductor device including a capacitor having improved structural stability and enhanced capacitance, a contact region is formed on a surface portion of a semiconductor substrate. After a mold layer is formed on the substrate, a st... | 10/24/2006 |
| 7115935 | Embedded DRAM for metal-insulator-metal (MIM) capacitor structure A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a log... | 10/03/2006 |
| 6700152 | Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is incr... | 03/02/2004 |
| 6696716 | Structures and methods for enhancing capacitors in integrated ciruits Systems, devices, structures, and methods are described that inhibit dielectric degradation in the presence of contaminants. An enhanced capacitor in a dynamic random access memory cell is discussed. The enhanced capacitor includes a first electrode, a di... | 02/24/2004 |
| 6661699 | Random access memory cell having double-gate access transistor for reduced leakage current A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel reg... | 12/09/2003 |
| 6661702 | Double gate DRAM memory cell having reduced leakage current A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel reg... | 12/09/2003 |
| 6660536 | Method of making ferroelectric material utilizing anneal in an electrical field A ferroelectric thin film precursor material is annealed while in an electric field. The electric field is maintained as the material cools. A partially completed integrated circuit with a ferroelectric thin film precursor material may be placed between t... | 12/09/2003 |
| 6649467 | Method of making high density semiconductor memory A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM memory cells are formed by transistor s... | 11/18/2003 |
| 6645807 | Method for manufacturing semiconductor device After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer.... | 11/11/2003 |
| 6635917 | Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts Semiconductor processing methods include forming a plurality of patterned device outlines over a semiconductor substrate, forming electrically insulative partitions or spacers on at least a portion of the patterned device outlines, and forming a plurality... | 10/21/2003 |
| 6627496 | Process for producing structured layers, process for producing components of an integrated circuit, and process for producing a memory configuration A process for producing structured layers on a base body, in particular a semiconductor body, includes the steps of providing a first layer, structuring the first layer with a partial or complete local layer erosion to form raised and recessed layer regio... | 09/30/2003 |
