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| Number | Title | Issue Date |
| 7382017 | Nano-enabled memory devices and anisotropic charge carrying arrays Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is de... | 06/03/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7355240 | Semiconductor product including logic, non-volatile memory and volatile memory devices and method for fabrication thereof A semiconductor product and a method for fabricating the semiconductor product employ a semiconductor substrate. The semiconductor substrate has a logic region having a logic device formed therein, a non-volatile memory region having a non-volatile memory device for... | 04/08/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7323349 | Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the... | 01/29/2008 |
| 7285813 | Metal-insulator-metal capacitor and method for manufacturing the same A capacitor has a lower electrode formed on an insulation layer, a dielectric layer formed on the lower electrode, an upper electrode layer formed on the dielectric layer, and a first protection layer pattern formed on the upper electrode layer. The upper electrode ... | 10/23/2007 |
| 7183595 | Ferroelectric memory A ferroelectric memory has a plurality of memory cells each having a transistor and a ferroelectric capacitor arranged in a matrix. Plate lines run in the word line direction above the ferroelectric capacitors of memory cells adjacent to each other in the word line ... | 02/27/2007 |
| 7126181 | Capacitor constructions The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and ... | 10/24/2006 |
| 6861689 | One transistor DRAM cell structure and method for forming A single transistor DRAM cell is formed in a SOI substrate so that the DRAM cells are formed in bodies that are electrically isolated from each other. Each cell has doped regions that act as source and drain contacts. Between the drain contact and the body is a regi... | 03/01/2005 |
| 6696867 | Voltage generator with stability indicator circuit A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 02/24/2004 |
| 6686786 | Voltage generator stability indicator circuit A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 02/03/2004 |
| 6680872 | Virtual ground semiconductor memory device A semiconductor memory device includes: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said m... | 01/20/2004 |
| 6674310 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 01/06/2004 |
| 6670664 | Single transistor random access memory (1T-RAM) cell with dual threshold voltages A random access memory cell and a method for fabrication thereof provide a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate. Within the random... | 12/30/2003 |
| 6664589 | Technique to control tunneling currents in DRAM capacitors, cells, and devices Structure and methods for the use of PMOS devices, with p-type polysilicon gates or metal gates with large electron affinities or work functions are provided. These PMOS devices minimize tunneling leakage currents in DRAM capacitors, cells and devices, as... | 12/16/2003 |
| 6664115 | Metal insulator structure with polarization-compatible buffer layer An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontiu... | 12/16/2003 |
| 6656781 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, HAVING FIRST AND SECOND SEMICONDUCTOR REGIONS WITH FIELD SHIELD ISOLATION STRUCTURES AND A FIELD OXIDE FILM COVERING A JUNCTION BETWEEN SEMICONDUCTOR REGIONS A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover th... | 12/02/2003 |
| 6649467 | Method of making high density semiconductor memory A dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells. The DRAM memory cells are formed by transistor s... | 11/18/2003 |
| 6638817 | Method for fabricating dram cell array not requiring a device isolation layer between cells The present invention relates to a DRAM cell array and a fabrication method thereof, and which includes: a semiconductor substrate on which a plurality of active regions and isolation regions in a rectangular strip shape at a predetermined distance from e... | 10/28/2003 |
| 6631084 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 10/07/2003 |
| 6627934 | Integrated semiconductor memory configuration with a buried plate electrode and method for its fabrication A semiconductor memory configuration has a plurality of selection transistors. Each selection transistor is connected to a first electrode of a storage capacitor. A second electrode of the storage capacitor is connected to a common plate. The common plate... | 09/30/2003 |
| 6620703 | Method of forming an integrated circuit using an isolation trench having a cavity formed by reflowing a doped glass mask layer Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF.... | 09/16/2003 |
| 6620674 | Semiconductor device with self-aligned contact and its manufacture A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the sec... | 09/16/2003 |
| 6611022 | Semiconductor thin film and its manufacturing method and semiconductor device and its manufacturing method A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having ... | 08/26/2003 |
| 6597206 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 07/22/2003 |
| 6597599 | Semiconductor memory In a semiconductor memory in which memory cells where a bit line is connected with the impurity diffused area of MOS transistors are arranged in a close packed layout in order to reduce the gate capacitance and junction capacitance of the impurity diffuse... | 07/22/2003 |
| 6594168 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 07/15/2003 |
| 6584010 | Selective device coupling Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conducta... | 06/24/2003 |
| 6583495 | Variable capacitor and memory device employing the same A variable capacitor and a memory device employing the same. The variable capacitor includes a first electrode formed above a substrate; a second electrode suspended with respect to the first electrode to be moved back and forth with respect to the first ... | 06/24/2003 |
| 6580631 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 06/17/2003 |
| 6574136 | Reduced leakage memory cell A random access memory cell (10) includes a first conductor line (12) and a second conductor line (14). A native device (16) is arranged to store charge. A high voltage threshold transistor (30) couples the native device to the first and second conductors... | 06/03/2003 |
| 6566206 | Semiconductor structure having more usable substrate area and method for forming same A semiconductor structure includes a first substrate portion having a surface and a first active region disposed in the first substrate portion. An insulator region is disposed on the first substrate portion outside of the first active region and extends ... | 05/20/2003 |
| 6559469 | Ferroelectric and high dielectric constant transistors An integrated circuit includes a layered superlattice material having the formula A1w1+a1 A2w2+a2 . . . Ajwj+aj S1x1+s1 S2x2+s2 . . . Skxk | 05/06/2003 |
| 6559032 | Method of fabricating an isolation structure on a semiconductor substrate A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is dep... | 05/06/2003 |
| 6560134 | Memory configuration with a central connection area A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of... | 05/06/2003 |
| 6556065 | 256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adja... | 04/29/2003 |
| 6548846 | Storage capacitor for a DRAM A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the con... | 04/15/2003 |
| 6537830 | Method of making ferroelectric FET with polycrystalline crystallographically oriented ferroelectric material A nondestructive read-out, nonvolatile ferroelectric field effect transistor ("FET") memory in an integrated circuit, containing a thin film of polycrystalline crystallographically oriented ferroelectric material. Preferably, the material is polycrystalli... | 03/25/2003 |
| 6504742 | 3-D memory device for large storage capacity A random access memory (memory) includes one or more planes of memory arrays stacked on top of each other. Each plane may be manufactured separately, and each array within the plane may be enabled/disabled separately. In this manner, each memory array wit... | 01/07/2003 |
| 6496408 | Selective device coupling Memory devices and other integrated circuit devices having a first capacitor and a second capacitor with an interposing selective isolation device, and methods of their operation. A selective isolation device is a device selectively in a state of conducta... | 12/17/2002 |
