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| Number | Title | Issue Date |
| 7439126 | Method for manufacturing semiconductor memory A method for manufacturing a semiconductor memory having a memory cell selection transistor and a capacitor, comprises a step of forming a polysilicon plug having a large-diameter portion on a side of the capacitor, a step of forming a hole reaching the large-diamet... | 10/21/2008 |
| 7439566 | Semiconductor memory device having metal-insulator transition film resistor A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a f... | 10/21/2008 |
| 7432548 | Silicon lanthanide oxynitride films Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or m... | 10/07/2008 |
| 7417285 | Semiconductor device having a trench capacitor and a MOSFET connected by a diffusion layer and manufacturing method thereof A semiconductor device comprises a semiconductor substrate having a first conductivity type, a trench capacitor, provided in the semiconductor substrate, having a charge storage region, a gate electrode provided on the semiconductor substrate via a gate insulating f... | 08/26/2008 |
| 7414278 | Semiconductor device with shallow trench isolation which controls mechanical stresses The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a s... | 08/19/2008 |
| 7391070 | Semiconductor structures and memory device constructions The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and ... | 06/24/2008 |
| 7385242 | Semiconductor device having landing pad and fabrication method thereof A semiconductor device can be provided comprising a semiconductor substrate having an upper surface. A plurality of adjacent line patterns are formed on the upper surface of the semiconductor substrate. Each line pattern includes a line having a capping layer patter... | 06/10/2008 |
| 7385235 | Spacer chalcogenide memory device The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings. ... | 06/10/2008 |
| 7384847 | Methods of forming DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array fabrication, with the etch stop covering storage node contact locations while leaving openings to bitline contact... | 06/10/2008 |
| 7378703 | Semiconductor device having step gates and method for fabricating the same The semiconductor device includes a substrate including a first active region and a second active region having a greater height than that of the first active region. A gate pattern has a step structure, which is formed on a border region between the first active re... | 05/27/2008 |
| 7371645 | Method of manufacturing a field effect transistor device with recessed channel and corner gate device Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A pr... | 05/13/2008 |
| 7368774 | Capacitor and its manufacturing method, ferroelectric memory device, actuator, and liquid jetting head A capacitor includes a lower electrode, a first dielectric film composed of lead zirconate titanate niobate formed above the lower electrode, a second dielectric film composed of lead zirconate titanate or lead zirconate titanate niobate with a Nb composition smalle... | 05/06/2008 |
| 7368752 | DRAM memory cell A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/... | 05/06/2008 |
| 7365384 | Trench buried bit line memory devices and methods thereof A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermo... | 04/29/2008 |
| 7355230 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access ... | 04/08/2008 |
| 7352018 | Non-volatile memory cells and methods for fabricating non-volatile memory cells The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory... | 04/01/2008 |
| 7339223 | Semiconductor devices having dual capping layer patterns and methods of manufacturing the same Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked ther... | 03/04/2008 |
| 7339222 | Method for determining wordline critical dimension in a memory array and related structure According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between tw... | 03/04/2008 |
| 7338868 | Method for forming gate oxide layer in semiconductor device A method for forming gate oxide layers of a semiconductor device including defining a first, a second, and a third device region by forming device isolation regions on a semiconductor substrate. The method also includes forming a sacrificing dielectric layer on the ... | 03/04/2008 |
| 7335934 | Integrated circuit device, and method of fabricating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, int... | 02/26/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7332767 | High density memory devices having improved channel widths and cell size A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current p... | 02/19/2008 |
| 7329919 | Non-volatile memory device and method of manufacturing the same A non-volatile memory device and a method of manufacturing the same where the non-volatile memory device is easily applicable to higher integration of a semiconductor device by reducing a cell size while assuring storage capacities required for operations of a devic... | 02/12/2008 |
| 7326985 | Method for fabricating metallic bit-line contacts A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between th... | 02/05/2008 |
| 7323349 | Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the... | 01/29/2008 |
| 7321144 | Semiconductor device employing buried insulating layer and method of fabricating the same A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silic... | 01/22/2008 |
| 7317220 | Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth A semiconductor assembly providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices is disclosed. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semicon... | 01/08/2008 |
| 7294879 | Vertical MOSFET with dual work function materials A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical p... | 11/13/2007 |
| 7291556 | Method for forming small features in microelectronic devices using sacrificial layers A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A cond... | 11/06/2007 |
| 7271433 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 09/18/2007 |
| 7265050 | Methods for fabricating memory devices using sacrificial layers A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elem... | 09/04/2007 |
| 7262452 | Method of forming DRAM device having capacitor and DRAM device so formed In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate... | 08/28/2007 |
| 7262053 | Terraced film stack A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses etch undercut resulting from materials of different etch selectivity used in the film stack,... | 08/28/2007 |
| 7259415 | Long retention time single transistor vertical memory gain cell A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lowe... | 08/21/2007 |
| 7242057 | Vertical transistor structures having vertical-surrounding-gates with self-aligned features The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with self-aligning features. The method provides process steps to define the transistor channel length and recess silico... | 07/10/2007 |
| 7242060 | Semiconductor memory device including an SOI substrate A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located bet... | 07/10/2007 |
| 7235835 | Semiconductor device and its manufacturing method, and electronic device The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS t... | 06/26/2007 |
| 7229881 | Dynamic random access memory of semiconductor device and method for manufacturing the same The present invention discloses an improved DRAM of semiconductor device and method for manufacturing the same wherein an ONO (oxide-nitride-oxide) structure for trapping electrons or holes used in a non-volatile memory is employed in a gate insulating film of the D... | 06/12/2007 |
| 7226845 | Semiconductor constructions, and methods of forming capacitor devices The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conduc... | 06/05/2007 |
| 7223693 | Methods for fabricating memory devices using sacrificial layers and memory devices fabricated by same Methods are provided for fabricating contacts in integrated circuit devices, such as phase-change memories. A protection layer and a sacrificial layer are sequentially formed on a semiconductor substrate. A contact hole is formed through the sacrificial layer and th... | 05/29/2007 |
