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| Number | Title | Issue Date |
| 7416945 | Method for forming a split gate memory device A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial ... | 08/26/2008 |
| 7375402 | Method and apparatus for increasing stability of MOS memory cells In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the ... | 05/20/2008 |
| 7352060 | Multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring substrate A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler i... | 04/01/2008 |
| 7332790 | Semiconductor device having an active area partially isolated by a lateral cavity A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area ... | 02/19/2008 |
| 7307332 | Semiconductor device and method for fabricating the same The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the sidewall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate ele... | 12/11/2007 |
| 7282757 | MIM capacitor structure and method of manufacture A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor devic... | 10/16/2007 |
| 7282803 | Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed be... | 10/16/2007 |
| 7274075 | Nonvolatile semiconductor memory device having pair of selection transistors with different source and drain impurity concentrations and with different channel dopant concentrations A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, an... | 09/25/2007 |
| 7244985 | Non-volatile memory array A non-volatile memory array including memory units which are arranged in a row/column array is provided. Source lines are arranged in parallel in the column direction and connect to the source regions of the memory units in the same column. Bit lines are arranged in... | 07/17/2007 |
| 7239002 | Integrated circuit device In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An ... | 07/03/2007 |
| 7235837 | Technique to control tunneling currents in DRAM capacitors, cells, and devices Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as gates. A memory cell is provided that utilizes materials with work functions larger than n-type doped po... | 06/26/2007 |
| 7075137 | Semiconductor memory having charge trapping memory cells In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations ... | 07/11/2006 |
| 6815762 | Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conduc... | 11/09/2004 |
| 6703656 | Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in a 12" wafer Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved f... | 03/09/2004 |
| 6703670 | Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention ... | 03/09/2004 |
| 6703658 | Non-volatile semiconductor memory device and its manufacturing method In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a fi... | 03/09/2004 |
| 6700168 | Layout structure and method of a column path of a semiconductor memory device A layout structure of column pass transistors of a semiconductor memory device, in which the area occupied with the transistors is reduced. Thus, in spite of high integration of the semiconductor memory device and miniaturization of memory cells, column p... | 03/02/2004 |
| 6699761 | Method for fabricating y-direction, self-alignment mask ROM device A method for fabricating a y-direction, self-alignment mask ROM device is described. The method includes forming a buried drain region in a substrate and forming a gate oxide layer on the substrate. Perpendicular to the direction of the buried drain regio... | 03/02/2004 |
| 6700165 | Semiconductor structure with the common source line A semiconductor structure with common source line, the semiconductor structure has two word lines, some bit lines, a silicon-based layer and a suicide layer. The silicon-based layer is located between and electrically separated from these word lines, but ... | 03/02/2004 |
| 6700201 | Reduction of sector connecting line capacitance using staggered metal lines In a memory array, a plurality of sectors are included. Each sector includes a plurality of parallel bit lines which lie in a plane. Sector connecting lines connect the sectors. These sector connecting lines are parallel to each other and to the bit lines... | 03/02/2004 |
| 6700143 | Dummy structures that protect circuit elements during polishing Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.... | 03/02/2004 |
| 6696329 | Method of manufacturing semiconductor device A silicon oxide film is formed by thermal oxidation on condition that the thickness thereof on the surface of a diffusion layer is about 3 nm. As a result, the silicon oxide film with a thickness of about 12 nm is formed on the surface of a source diffusi... | 02/24/2004 |
| 6696340 | Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same A method for manufacturing a semiconductor device having a non-volatile memory transistor may include the steps of forming a floating gate 22 over a semiconductor layer 10 through a first insulation layer 20, forming a second insulation layer 26 that cont... | 02/24/2004 |
| 6690051 | FLASH memory circuitry FLASH memory circuitry includes an array area and peripheral circuitry area. Multiple series of spaced isolation trenches are provided. At least one of the series of spaced trench isolation regions is formed in a semiconductor substrate within the FLASH p... | 02/10/2004 |
| 6690053 | Shared contact in a semiconductor device in which DRAMs and SRAMs are combined and method of manufacturing the same The semiconductor device according to the present invention comprises side wall 9 formed over the sidewall of gate wiring 6 of a logic SRAM region, doped polysilicon 18 electrically connecting silicide layer 13 formed over the surface of diffused layer 11... | 02/10/2004 |
| 6690603 | Microcomputer including a flash memory that is two-way programmable A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective... | 02/10/2004 |
| 6686242 | Method for producing metallic bit lines for memory cell arrays, method for producing memory cell arrays and memory cell array A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on ... | 02/03/2004 |
| 6686618 | Semiconductor memory having a plurality of memory-cell arrays The invention relates to a semiconductor memory (1) having a plurality of memory-cell arrays (2), a plurality of sense-amplifier areas (3) and a plurality of driver areas (4) on a semiconductor substrate (7) of a first conductivity type, each of the multi... | 02/03/2004 |
| 6683365 | Edge intensive antifuse device structure An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantial... | 01/27/2004 |
| 6683342 | Memory structure and method for manufacturing the same A memory structure and the method for fabricating the same are disclosed in this present invention. A first gate structure and a second gate structure are provided onto a substrate. After an implanting process, the first gate structure will become the per... | 01/27/2004 |
| 6680227 | Non-volatile memory device and fabrication method thereof A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed ... | 01/20/2004 |
| 6680230 | Semiconductor device and method of fabricating the same A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. T... | 01/20/2004 |
| 6674112 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a semiconductor substrate and operates when supplied with appositive supply voltage and a circuit ground potential. The device has word lines, pairs of bit lines, data storage capacitors, and N-channel MOSFETs... | 01/06/2004 |
| 6674118 | PIP capacitor for split-gate flash process A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floati... | 01/06/2004 |
| 6674110 | Single transistor ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric A single transistor ("1T") ferroelectric memory cell, device and method for the formation of the same incorporating a high temperature ferroelectric gate dielectric. The memory cell of the present invention comprises a substrate, an overlying ferroelectri... | 01/06/2004 |
| 6670234 | Method of integrating volatile and non-volatile memory cells on the same substrate and a semiconductor memory device thereof A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are elec... | 12/30/2003 |
| 6671202 | Programmable circuit structures with reduced susceptibility to single event upsets Programmable circuit structures having reduced susceptibility to single event upsets. A circuit structure includes a programmable circuit controlled by a group of memory cells, of which at most one has an enable value. The memory cells are coupled togethe... | 12/30/2003 |
| 6670227 | Method for fabricating devices in core and periphery semiconductor regions using dual spacers For fabricating a first device within a core region and a second device within a periphery region, of a semiconductor substrate, disposable spacers having a first width are formed at sidewalls of a first gate stack of the core region and a second gate sta... | 12/30/2003 |
| 6667212 | Alignment system for planar charge trapping dielectric memory cell lithography A method of fabricating a charge trapping dielectric memory cell array comprises exposing a first photoresist to a first illumination pattern from a first mask to pattern bit line regions in a core region of the wafer and to pattern alignment mark regions... | 12/23/2003 |
| 6667507 | Flash memory having memory section and peripheral circuit section A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided o... | 12/23/2003 |
