Class 257/E27.078 - Bipolar electrically programmable memory structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 42
Last issue date: 10/28/2008

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Number	Title	Issue Date
7442987	Non-volatile memory devices including divided charge storage structures A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel ...	10/28/2008
7420243	Non-volatile memory device with buried control gate and method of fabricating the same In a non-volatile memory device with a buried control gate, the effective channel length of the control gate is increased to restrain punchthrough, and a region for storing charge is increased for attaining favorably large capacity. A method of fabricating the memor...	09/02/2008
7391078	Non-volatile memory and manufacturing and operating method thereof A non-volatile memory is provided. A substrate having a plurality of trenches and a plurality of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjace...	06/24/2008
7385244	Flash memory devices with box shaped polygate structures A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching ...	06/10/2008
7355243	Flash memory device and method for fabricating the same A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region ...	04/08/2008
7345335	Semiconductor integrated circuit, booster circuitry, and non-volatile semiconductor memory device In a capacitor-containing semiconductor integrated circuit, a portion in which a plurality of capacitors are serially connected together is arranged so that at least part of the capacitors is formed as a well capacitor. ...	03/18/2008
7332789	Isolation trenches for memory devices Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first diele...	02/19/2008
7323349	Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the...	01/29/2008
7312496	Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single g...	12/25/2007
7304345	Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a float...	12/04/2007
7301196	Nonvolatile memories and methods of fabrication In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floa...	11/27/2007
7253470	Floating gate with unique profile by means of undercutting for split-gate flash memory device A split-gate flash memory device has a floating gate with a lateral recess at its bottom sidewall by adding an undercutting step. The split-gate flash memory device has a floating gate with a lateral recess on a substrate, an integrated dielectric layer lining the s...	08/07/2007
7122853	Method to improve yield and simplify operation of polymer memory cells Systems and methodologies are provided for simplifying a polymer memory cell's operation by employing a post polymer growth treatment to form ionic or super ionic metal compounds therein. Such post polymer growth treatment facilitates distribution and mobility of me...	10/17/2006
6995436	Nonvolatile semiconductor memory device In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to ...	02/07/2006
5595920	Method of manufacturing a semiconductor memory device for use with image pickup A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate elect...	01/21/1997
5567962	Semiconductor memory device A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate elect...	10/22/1996
5436496	Vertical fuse device A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emit...	07/25/1995
5331197	Semiconductor memory device including gate electrode sandwiching a channel region A semiconductor memory device includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between the plurality of main electrode regions, and a gate elect...	07/19/1994
5212102	Method of making polysilicon Schottky clamped transistor and vertical fuse devices An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The im...	05/18/1993
5144404	Polysilicon Schottky clamped transistor and vertical fuse devices An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The im...	09/01/1992
4961102	Junction programmable vertical transistor with high performance transistor An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to th...	10/02/1990
4949150	Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers The present invention is a bonding pad structure and method for making the same which can be connected at the metalization step to form passive or active devices in addition to forming a bonding pad. A P-doped region is formed in an epitaxial layer in the...	08/14/1990
4835590	Semiconductor memory device using junction short type programmable element A semiconductor memory device using a junction short type programmable element comprises an epitaxial layer formed on a semiconductor substrate, the epitaxial layer having an opposite conductive type to that of the semiconductor substrate, the epitaxial l...	05/30/1989
4805141	Bipolar PROM having transistors with reduced base widths A semiconductor device having a vertical transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector, a base, and an emitter of a transistor. By providing a hig...	02/14/1989
4792833	Junction-shorting type semiconductor read-only memory having increased speed and increased integration density In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface t...	12/20/1988
4782466	Programmable semiconductor read only memory device A programmable semiconductor read only memory device which includes a memory cell array formed by a plurality of memory cells arranged in a matrix arrangement. Each memory cell in the memory cell array includes a transistor having a gate thereof coupled t...	11/01/1988
4719599	Programmable read-only memory device provided with test cells A programmable read-only memory device of a junction destruction type is provided with a test circuit for the purpose of detecting a parasitic thyristor effect which may occur in the data programming operation by the user. The test circuit includes first ...	01/12/1988
4654688	Semiconductor device having a transistor with increased current amplification factor A semiconductor device having a lateral transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector, a base, and an emitter of a transistor. By providing a high...	03/31/1987
4624046	Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM An oxide-isolated RAM and PROM process is disclosed wherein a RAM circuit includes a lateral PNP transistor formed in the same island of silicon material as a vertical NPN device and further wherein contact is made to the base of the lateral PNP and to th...	11/25/1986
4536858	Junction short-circuiting-type programmable read-only memory device A junction short-circuiting-type programmable read-only memory (PROM) device comprises a plurality of striped buried layers (12) and a plurality of striped collector regions (13) thereon. In each of the collector regions, a plurality of base regions (15-0...	08/20/1985
4480318	Method of programming of junction-programmable read-only memories A method of programming a cell in a PROM, wherein the cell comprises a bipolar transistor having a floating base, comprises applying a current rising with time across the emitter to collector contacts of the bipolar transistor with the collector contact s...	10/30/1984
4453233	Semiconductor memory device and method of manufacturing the same A programmable semiconductor memory device with an emitter follower type poly-silicon fuse comprises: a first semiconductor region of first conductivity type; a first insulation layer for separating elements formed in the first semiconductor region; a sec...	06/05/1984
4412308	Programmable bipolar structures A switchable bipolar structure, suitable for use in a programmable read only memory, is provided which includes a rectifying contact disposed on a N type semiconductor substrate with a P type diffusion region formed in the substrate spaced within a minori...	10/25/1983
4329703	Lateral PNP transistor Shallow, boron implanted regions are formed by ion implanting. Disclosed is a PNP transistor device (lateral type) having a P type emitter region preferably made with a boron implant....	05/11/1982
4312046	Vertical fuse and method of fabrication In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is f...	01/19/1982
4287569	Semiconductor memory device In a semiconductor memory device having a plurality of memory cells located at a cross position of a plurality of bit lines and a plurality of word lines, the memory cell comprising a series circuit of an information storing element such as a diode or a f...	09/01/1981
4228451	High resistivity semiconductor resistor device This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense ampl...	10/14/1980
4196228	Fabrication of high resistivity semiconductor resistors by ion implanatation This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense ampl...	04/01/1980
4153949	Electrically programmable read-only-memory device A matrix of columns and rows of conductors with transistors located at the intersection thereof on a semiconductor chip is formed utilizing the washed emitter process which locates the ohmic contact windows close to the PN junction so that a small size pi...	05/08/1979
4152627	Low power write-once, read-only memory array This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense ampl...	05/01/1979

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Class 257/E27.078 - Bipolar electrically programmable memory structure (EPO)