Class 257/E27.077 - Static bipolar memory cell structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 84
Last issue date: 01/29/2008

«First «Previous1 2 3 Next»Last»

Number	Title	Issue Date
7323349	Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the...	01/29/2008
6292390	Semiconductor device A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE	09/18/2001
6232822	Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition IBE	05/15/2001
5502327	Semiconductor device A semiconductor device includes a first layer made of a first type semiconductor, a second layer provided on the first layer and made of a second type semiconductor, the second layer including low resistance diffusion parts and high resistance diffusion p...	03/26/1996
5471419	Semiconductor device having a programmable memory cell A semiconductor device having a programmable memory cell which includes a bipolar transistor of which a base region (13) can be provided with a base current through a control transistor (7, 8, 9, 10). The bipolar transistor has an emitter region (12) conn...	11/28/1995
5313090	Bipolar memory cell having capacitors A semiconductor device including a semiconductor substrate, first and second bipolar transistors formed at the major surface of the semiconductor substrate, a Schottky-barrier diode formed on a predetermined area of each of the first and second bipolar tr...	05/17/1994
5287303	SCR type memory apparatus An SCR type memory apparatus which is short in access time, easy in setting current values upon reading and writing and easy in constructing a peripheral circuit with less power supply voltage limitation is described. The semiconductor memory apparatus co...	02/15/1994
5276638	Bipolar memory cell with isolated PNP load A bipolar memory array and memory cell. The memory cell has a pair of cross coupled NPN storage transistors and a pair of PNP load transistors. The collector of each of the load transistors is connected to one of the storage transistors. A base, common to...	01/04/1994
5095355	Bipolar cross-coupled memory cells having improved immunity to soft errors A bipolar RAM comprising a plurality of memory cells formed of cross-coupled bipolar transistors and a peripheral bipolar circuit formed of bipolar transistor, provided with an epitaxial layer which is to be the collector region of the bipolar transistor ...	03/10/1992
5016075	Semiconductor memory device A semiconductor memory device is constructed of a lateral bipolar transistor as a load element. The base region of the lateral bipolar transistor has an impurity concentration which is increased from the upper surface of the base region in the depth direc...	05/14/1991
4992981	Double-ended memory cell array using interleaved bit lines and method of fabrication therefore The memory cell array is one in which the bit lines associated with each column of double-ended memory cells are interleaved with the bit lines of adjacent columns of memory cells. Because the spacing of metallic bit lines is governed by certain ground ru...	02/12/1991
4984196	High performance bipolar differential sense amplifier in a BiCMOS SRAM A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of ...	01/08/1991
4981807	Process for fabricating complementary vertical transistor memory cell A compact complementary transistor switch (CTS) memory cell structure utilizing both vertical PNP and vertical NPN transistors in gallium arsenide technology is described. The base region of the vertical PNP transistor merges with the collector region of ...	01/01/1991
4958320	Radiation resistant bipolar memory A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means fo...	09/18/1990
4956688	Radiation resistant bipolar memory A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arran...	09/11/1990
4954455	Semiconductor memory device having protection against alpha strike induced errors The invention comprises an improved bipolar memory device having enhanced protection against the effects of alpha particles comprising at least one memory cell having a buried layer forming at least a portion of the collector of one of the transistors in ...	09/04/1990
4905078	Semiconductor device A semiconductor device includes a semiconductor layer provided above a pair of bipolar transistors formed in a surface region of a semiconductor body. Schottky barrier diodes and resistors are formed in the semiconductor layer. The pair of bipolar transis...	02/27/1990
4829361	Semiconductor device A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a re...	05/09/1989
4815037	Bipolar type static memory cell A bipolar type static memory cell comprising two cross connected circuits, each of the circuits including a transistor and a load element is disclosed. An N-type epitaxial layer, grown on an N+ -type buried layer, is used as a collector region ...	03/21/1989
4813017	Semiconductor memory device and array A memory array fabricated on a silicon substrate consists of memory cells each having two lateral p-n-p load-injector transistors and two vertical n-p-n flip-flop transistors with the p-n-p's being formed in a portion of the substrate which is electricall...	03/14/1989
4809052	Semiconductor memory device A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the me...	02/28/1989
4807008	Static memory cell using a heterostructure complementary transistor switch A heterostructure complementary transistor switch (HCTS) is fabricated using epitaxial layers on a substrate to form the desired P-N-P-N (or N-P-N-P) complementary structure in III-V compound semiconductor materials. Two HCTS are formed on a single substr...	02/21/1989
4799089	Semiconductor memory device A semiconductor memory device, in which many memory cells formed by transistors having a Schottky barrier transistor as a load are arranged along word lines and the memory cells are driven from one end of the word lines by word drivers. Dummy cells are fo...	01/17/1989
4785342	Static random access memory having structure of first-, second- and third-level conductive films A resistance element having a reduced occupied area and a high resistance which may be employed as a load resistor used in, for example, a static memory device. A high-resistance area is formed using a relatively thin film, while an interconnection area i...	11/15/1988
4714842	Integrated injection logic circuits An "Integrated Injection Logic" integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via...	12/22/1987
4677455	Semiconductor memory device In a semiconductor memory cell having PNPN type memory cells, a vertical PNPN element is used as a load transistor and a sense transistor or a hold transistor, or both. A buried layer is used as a wiring layer for a word line or a bit line, so that the sw...	06/30/1987
4669180	Method of forming emitter coupled logic bipolar memory cell using polysilicon Schottky diodes for coupling An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of t...	06/02/1987
4656495	Bipolar ram cell and process An integrated bipolar RAM cell and process for its manufacture is disclosed. The RAM cell includes first and second cross-coupled bipolar transistors with first and second load elements coupled to the collectors of the first and second transistors, respec...	04/07/1987
4654824	Emitter coupled logic bipolar memory cell An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of t...	03/31/1987
4636833	Semiconductor device A semiconductor device comprising a first electrode, a dielectric film and a second electrode which are stacked and formed on a semiconductor layer with the second electrode in contact with the semiconductor layer. A diode is formed of the second electrod...	01/13/1987
4635087	Monolithic bipolar SCR memory cell Bipolar memory arrays having lower quiescent leakage and higher switching speed are constructed by using coupled SCRs formed from vertical PNP and NPN devices. Buried collectors for the PNP and NPN devices are provided within the same isolation tub. A P t...	01/06/1987
4635230	Emitter coupled logic bipolar memory cell An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of t...	01/06/1987
4624863	Method of fabricating Schottky diodes and electrical interconnections in semiconductor structures A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the ...	11/25/1986
4622575	Integrated circuit bipolar memory cell A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silico...	11/11/1986
4589096	IIL semiconductor memory including arrangement for preventing information loss during read-out A semiconductor memory having memory cells in each of which emitter terminals and first collector terminals of two IIL unit circuits are cross-connected to each other, injector regions and a common emitter region of the two IIL unit circuits are respectiv...	05/13/1986
4550390	Semiconductor memory device A semiconductor memory having a construction making it less susceptible to ଱-rays. The memory includes a pair of transistors connected in a flip-flop arrangement. In each memory transistor there is a buried region of high concentration which contact...	10/29/1985
4543595	Bipolar memory cell A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the ...	09/24/1985
4538244	Semiconductor memory device A semiconductor memory device in which a bipolar memory cell includes two cross-coupled transistors. The collector load is a Schottky barrier diode. A capacitor is formed to be connected to the Schottky barrier diode. The capacitor is formed by a junction...	08/27/1985
4535425	Highly integrated, high-speed memory with bipolar transistors A memory is described comprising static MTL memory cells for high operation speeds. The cell or primary injectors and the bit line injectors are coupled to each other by an angular injection coupling via the low-resistivity base region of the cell flip-fl...	08/13/1985
4488350	Method of making an integrated circuit bipolar memory cell A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silico...	12/18/1984

«First «Previous1 2 3 Next»Last»

PatentStorm

Did You Know...

PatentStorm News

Class 257/E27.077 - Static bipolar memory cell structure (EPO)