Class 257/E27.075 - Bipolar dynamic random access memory structure (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 23
Last issue date: 07/01/2008

Number	Title	Issue Date
7393739	Demultiplexers using transistors for accessing memory cell arrays A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2N semiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in...	07/01/2008
7323349	Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the...	01/29/2008
7105900	Reduced floating body effect static random access memory cells and methods for fabricating the same An SRAM cell that may reduce or eliminate floating body effect when using a SOI and a method for fabricating the same are provided. A floating body of an access transistor of the SRAM is connected to a source region of a driver transistor, for example, through a bod...	09/12/2006
5883406	High-speed and high-density semiconductor memory A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in t...	03/16/1999
5808328	High-speed and high-density semiconductor memory A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in t...	09/15/1998
5471087	Semi-monolithic memory with high-density cell configurations A memory is formed from an array of switchless integrated circuit memory cells in a high-density configuration. These cells comprise a capacitor and two diodes in a configuration where one diode is used to charge one pole of the capacitor, and the other d...	11/28/1995
5465249	Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate A random access memory (RAM) cell in 6H-SiC having storage times when all bias is removed long enough to be considered nonvolatile. The nonvolatile random access memory (NVRAM) cell comprises a bit line, a charge storage device in silicon carbide, and a t...	11/07/1995
5391912	Semiconductor device having polycrystalline silicon region forming a lead-out electrode region and extended beneath active region of transistor This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is (111) is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral...	02/21/1995
5365477	Dynamic random access memory device A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, with ...	11/15/1994
5296731	Semiconductor integrated circuit device with alpha rays resistance A semiconductor integrated circuit device according to the present invention includes a semiconductor layer of a first conductivity type having a high concentration of impurity atoms which layer is formed in or on predetermined locations of a semiconducto...	03/22/1994
5262670	Vertically stacked bipolar dynamic random access memory A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switchin...	11/16/1993
5227660	Semiconductor device This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is a (111) plane is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a...	07/13/1993
5132748	Semiconductor memory device A semiconductor device includes a first semiconductor region connected to a bit line for controlling signal charges; a second semiconductor region connected to the first semiconductor region and to a word line for controlling signal charges, wherein the s...	07/21/1992
4994999	High-speed and high-density semiconductor memory A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in t...	02/19/1991
4704368	Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed ...	11/03/1987
4476623	Method of fabricating a bipolar dynamic memory cell This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP t...	10/16/1984
4434433	Enhancement mode JFET dynamic memory A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in t...	02/28/1984
4427989	High density memory cell A dynamic memory cell has a P+ injector region surrounded by an N+ region in an N- layer on an N+ layer. The injector region is placed between N+ source and drain regions. Holes injected into the N-layer are trapped by the high-low junctions at the N+, N-...	01/24/1984
4309716	Bipolar dynamic memory cell This describes a novel bipolar dynamic cell array with increased dielectric node capacitance and a method of making it. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node capacitance of the PNP t...	01/05/1982
4190466	Method for making a bipolar transistor structure utilizing self-passivating diffusion sources A semiconductor structure, formed within a recessed oxide isolation region, includes a semiconductor substrate of a first conductivity type within which a collector of opposite conductivity type is formed below the surface of the substrate and extending i...	02/26/1980
4181981	Bipolar two device dynamic memory cell This describes a novel bipolar dynamic cell especially useful as a Random Access Memory Cell. In the described cell a PNP transistor drives an NPN transistor so that information is stored at the base node of the PNP transistor. By using the PNP transistor...	01/01/1980
4090254	Charge injector transistor memory Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferrably in the capacitance of the juncti...	05/16/1978
3979734	Multiple element charge storage memory cell An integrated circuit memory system includes capacitive storage memory cells capable of storing n bits of information on n capacitors associated with multiple emitters of a bilaterally conductive bipolar transistor. Each capacitor is coupled to a separate...	09/07/1976

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Class 257/E27.075 - Bipolar dynamic random access memory structure (EPO)