Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7420228 | Bipolar transistor comprising carbon-doped semiconductor A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a s... | 09/02/2008 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 6218722 | Antifuse based on silicided polysilicon bipolar transistor An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic ste... | 04/17/2001 |
| 5920771 | Method of making antifuse based on silicided single polysilicon bipolar transistor An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic ste... | 07/06/1999 |
| 5661681 | Semiconductor memory and method of writing, reading, and sustaining data thereof A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emi... | 08/26/1997 |
| 5311465 | Semiconductor memory device that uses a negative differential resistance A semiconductor memory device comprises a memory cell transistor that includes two active parts each including therein an emitter and a base and showing a negative differential resistance. The collector layer is shared commonly by the two active parts and... | 05/10/1994 |
| 4466178 | Method of making extremely small area PNP lateral transistor by angled implant of deep trenches followed by refilling the same with dielectrics An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope th... | 08/21/1984 |
| 4429326 | I2 L Memory with nonvolatile storage An I2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I2 L... | 01/31/1984 |
| 4143421 | Tetrode transistor memory logic cell A memory cell, made of a tetrode type bipolar transistor, which has an emitter, a base, a collector, and a grid, insulated by a dielectric layer in which an insulated screen is arranged between the grid and the base, the operation as a memory cell requiri... | 03/06/1979 |
| 4130826 | Monolithic integrated semiconductor circuit A monolithic integrated semiconductor circuit including a plurality of low on-state resistance vertical bipolar switching transistors for connecting a series of input lines, as desired, to one or more output lines wherein each of said switching transistor... | 12/19/1978 |
| 4125855 | Integrated semiconductor crosspoint arrangement Symmetrical integrated transistors and drive circuitry provide low loss bilateral analog crosspoints for a switching matrix. Each crosspoint comprises a high performance PNP lateral transmission switching transistor and an associated NPN vertical drive tr... | 11/14/1978 |
| 4122542 | Memory array An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupl... | 10/24/1978 |
