"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7414274 | Selective oxidation of silicon in diode, TFT and monolithic three dimensional memory arrays The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of ... | 08/19/2008 |
| 7402855 | Split-channel antifuse array architecture Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technolo... | 07/22/2008 |
| 7381997 | Lateral silicided diodes A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the... | 06/03/2008 |
| 7339186 | IC chip with nanowires Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as trans... | 03/04/2008 |
| 7335927 | Lateral silicided diodes A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the... | 02/26/2008 |
| 6653712 | Three-dimensional memory array and method of fabrication A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is lo... | 11/25/2003 |
| 6653195 | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combinati... | 11/25/2003 |
| 6649928 | Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change ... | 11/18/2003 |
| 6631085 | Three-dimensional memory array incorporating serial chain diode stack A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each... | 10/07/2003 |
| 6624485 | Three-dimensional, mask-programmed read only memory A 3-dimensional read only memory includes vertically stacked layers of memory cells. Each of the memory cells includes a mask programmed insulating layer, a pair of diode components, and a pair of crossing-conductors. The conductors (other than those at t... | 09/23/2003 |
| 6605527 | Reduced area intersection between electrode and programming element A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defini... | 08/12/2003 |
| 6599796 | Apparatus and fabrication process to reduce crosstalk in pirm memory array A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plura... | 07/29/2003 |
| 6483736 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking ... | 11/19/2002 |
| 6429449 | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combinati... | 08/06/2002 |
| 6420215 | Three-dimensional memory array and method of fabrication A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.... | 07/16/2002 |
| 6392913 | Method of forming a polysilicon diode and devices incorporating such diode A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material... | 05/21/2002 |
| 6385074 | Integrated circuit structure including three-dimensional memory array An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supp... | 05/07/2002 |
| 6303975 | Low noise, high frequency solid state diode A low noise, high frequency solid state diode is provided from a plurality of unit diode cells which are interconnected in parallel. Each of the unit diode cells forms an element of an array having rows and columns of unit diode cells. The diode cells inc... | 10/16/2001 |
| 6252244 | Memory cell having a reduced active area and a memory array incorporating the same There is disclosed a memory cell having a reduced active area. The memory cell may be incorporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protru... | 06/26/2001 |
| 6236059 | Memory cell incorporating a chalcogenide element and method of making same A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disp... | 05/22/2001 |
| 6229157 | Method of forming a polysilicon diode and devices incorporating such diode A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material... | 05/08/2001 |
| 6225142 | Memory cell having a reduced active area and a memory array incorporating the same There is disclosed a memory cell having a reduced active area. The memory cell may be incorporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protru... | 05/01/2001 |
| 6215140 | Electrically programmable non-volatile memory cell configuration A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lin... | 04/10/2001 |
| 6194303 | Memory device A memory device consists of an array of resonant tunnel diodes in the form of pillars which are formed by selective etching. Each pillar includes first and second barriers (B1, B2) disposed between terminal regions (T1, T2) and a conductive region (CR1) b... | 02/27/2001 |
| 6185122 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking ... | 02/06/2001 |
| 6153890 | Memory cell incorporating a chalcogenide element A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disp... | 11/28/2000 |
| 6143610 | Method for fabricating high-density semiconductor read-only memory device A semiconductor read-only memory (ROM) device is provided and includes an array of diode-based memory cells for storing binary data. Whether a memory cell of the ROM device is set to a permanently-ON or OFF state, depends upon whether the memory cell is f... | 11/07/2000 |
| 6118135 | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combinati... | 09/12/2000 |
| 6087689 | Memory cell having a reduced active area and a memory array incorporating the same There is disclosed a memory cell having a reduced active area. The memory cell may be incoporated into a memory array. A method of fabricating the memory cell and the memory array includes the fabrication of an access device, such as a diode, that protrud... | 07/11/2000 |
| 6064100 | Product for ROM components having a silicon controlled rectifier structure A manufacturing method and a structure for ROM component having a silicon controlled rectifier as the basic memory instead of a channel transistor in a conventional ROM, and using a formation of contact windows for coding a ROM instead of performing an io... | 05/16/2000 |
| 6034882 | Vertically stacked field programmable nonvolatile memory and method of fabrication A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking ... | 03/07/2000 |
| 6028342 | ROM diode and a method of making the same A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon n... | 02/22/2000 |
| 6025220 | Method of forming a polysilicon diode and devices incorporating such diode A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material... | 02/15/2000 |
| 6018168 | Semiconductor memory devices having alternating word line reverse diodes and well bias tapping regions Semiconductor memory devices include a plurality of word line reverse diodes located at alternating ends of a plurality of parallel word lines. A plurality of well bias tapping regions are also located at alternating ends of the plurality of parallel word... | 01/25/2000 |
| 6015995 | ROM diode structure A read only memory device, which includes a P-type substrate, is provided. Several essentially parallel N-pole regions are located on the substrate. The N-pole regions extends in a first direction, and are separated from each other by a space. The N-pole ... | 01/18/2000 |
| 6015738 | Method for fabricating transistorless, multistable current-mode memory cells and memory arrays A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedan... | 01/18/2000 |
| 5998244 | Memory cell incorporating a chalcogenide element and method of making same A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disp... | 12/07/1999 |
| 5985698 | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combinati... | 11/16/1999 |
| 5970336 | Method of making memory cell incorporating a chalcogenide element A memory cell incorporating a chalcogenide element and a method of making same is disclosed. In the method, a doped silicon substrate is provided with two or more polysilicon plugs to form an array of diode memory cells. A layer of silicon nitride is disp... | 10/19/1999 |
| 5962900 | High-density diode-based read-only memory device A read-only memory (ROM) device of the type including an array of diode-based memory cells for permanent storage of binary-coded data. The ROM device is partitioned into a memory division and an output division. The memory cells are formed over an insulat... | 10/05/1999 |