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| Number | Title | Issue Date |
| 7442603 | Self-aligned structure and method for confining a melting point in a resistor random access memory A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying... | 10/28/2008 |
| 7388275 | Electronic package with integrated capacitor Generally provided is a circuit assembly construction for controlling impedance in an electronic package. A large scale, parallel-plate capacitor includes two electrodes separated by a dielectric material. The electrodes serve as reference voltage planes for the ele... | 06/17/2008 |
| 7371632 | Semiconductor device having high-voltage transistor and PIP capacitor and method for fabricating the same A semiconductor device having a high-voltage transistor and a polysilicon-insulator-polysilicon (PIP) capacitor, and a method for fabricating the same are provided. A current flow path of the high-voltage transistor is widened to reduce on-resistance of the device. ... | 05/13/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7348656 | Power semiconductor device with integrated passive component A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof. ... | 03/25/2008 |
| 7326987 | Non-continuous encapsulation layer for MIM capacitor The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Lin... | 02/05/2008 |
| 7321149 | Capacitor structures, and DRAM arrays A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking lay... | 01/22/2008 |
| 7298019 | Capacitor of semiconductor device and method of manufacturing the same A MIM capacitor includes a lower electrode disposed on a semiconductor substrate. A dielectric layer is disposed on the lower electrode to completely cover an exposed surface of the lower electrode. An upper electrode is disposed on the dielectric layer. A method fo... | 11/20/2007 |
| 7208388 | Thin film resistor head structure and method for reducing head resistivity variance A method of making integrated circuit thin film resistor includes forming a first dielectric layer (18B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (9A) on the first dielectr... | 04/24/2007 |
| 7209340 | Semiconductor device and MIM capacitor An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patte... | 04/24/2007 |
| 7176081 | Low temperature method for metal deposition A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a depo... | 02/13/2007 |
| 7126809 | Semiconductor device and MIM capacitor An MIM capacitor comprises first and second conductor patterns embedded in a first interlayer insulation film so as to extend continuously in a mutually opposing relationship and forming a part of a comb-shaped capacitor pattern, and third and fourth conductor patte... | 10/24/2006 |
| 7115938 | Non-volatile memory cell and method of forming the same A non-volatile memory cell comprising a transistor and two plane capacitors. In the memory cell, a switching device is disposed on a substrate, a first plane capacitor having a first doped region and a second plane capacitor having a second doped region. The switchi... | 10/03/2006 |
| 7102188 | High reliability electrically erasable and programmable read-only memory (EEPROM) An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the w... | 09/05/2006 |
| 7091542 | Method of forming a MIM capacitor for Cu BEOL application The present invention relates generally to integrated circuits, and particularly, but not by way of limitation, metal-insulator-metal (MIM) capacitors formed within a trench located within a metallization layer and in particular to MIM capacitors for Cu BEOL semicon... | 08/15/2006 |
| 6917063 | Ferroelectric memory and method of fabricating the same A ferroelectric memory includes a substrate and a sheet-shaped device formed over the substrate through an adhesive layer. The sheet-shaped device includes a memory cell array in which a ferroelectric layer is disposed at least in intersecting regions of a plurality... | 07/12/2005 |
| 6818966 | Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin f... | 11/16/2004 |
| 6703652 | Memory structure and method making A memory structure has a plurality of row conductors intersecting a plurality of column conductors at a plurality of intersections. Each intersection includes an electrically linear resistive element in series with a voltage breakdown element.... | 03/09/2004 |
| 6690599 | Ferroelectric memory device A ferroelectric memory device includes a simple matrix type memory cell array. Provided that the maximum absolute value of a voltage applied between a first signal electrode and a second signal electrode is Vs, polarization P of a ferroelectric capacitor ... | 02/10/2004 |
| 6673691 | Method for resistance switch using short electric pulses A method of changing the resistance of a perovskite metal oxide thin film device with a resistance-change-producing pulse includes changing the resistance of the device by varying the duration of a resistance-change-producing pulse.... | 01/06/2004 |
| 6664117 | Method for resistance memory metal oxide thin film deposition A method of forming a multi-layered, spin-coated perovskite thin film on a wafer includes preparing a perovskite precursor solution including mixing solid precursor material into acetic acid forming a mixed solution; heating the mixed solution in air for ... | 12/16/2003 |
| 6645809 | Process for producing a capacitor configuration In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a di... | 11/11/2003 |
| 6635914 | Microelectronic programmable device and methods of forming and programming the same A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered... | 10/21/2003 |
| 6617627 | Memory cell array having ferroelectric capacitors, method of fabricating the same, and ferroelectric memory device. The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a m... | 09/09/2003 |
| 6580144 | One time programmable fuse/anti-fuse combination based memory cell A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relativ... | 06/17/2003 |
| 6563164 | Compositionally modified resistive electrode An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a ... | 05/13/2003 |
| 6534368 | Integrated circuit memory cell having a small active area and method of forming same A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a s... | 03/18/2003 |
| 6532568 | Apparatus and method for conditioning polysilicon circuit elements An apparatus and method for conditioning polysilicon circuit elements includes a supply source configured to impress a desired voltage or current upon a polysilicon circuit element including at least a polysilicon resistor for a desired signal duration. T... | 03/11/2003 |
| 6518824 | Antifuse programmable resistor A user-programmable resistor module includes a resistive element connected in series with first and second antifuses between an input circuit node and an output circuit node. Third and fourth antifuses are connected in series between the input circuit nod... | 02/11/2003 |
| 6462512 | Capacitor storage system A capacitor storage system is provided which is simple in structure and can control the charge level according to the use environment and detect a fault, if any. The capacitor storage system comprises: a plurality of capacitors connected in series and pro... | 10/08/2002 |
| 6417043 | Memory cell configuration and fabrication method Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the pot... | 07/09/2002 |
| 6404665 | Compositionally modified resistive electrode An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor comprises a first material having a ... | 06/11/2002 |
| 6287919 | Integrated circuit memory cell having a small active area and method of forming same A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a s... | 09/11/2001 |
| 6281564 | Programmable integrated passive devices An integrated passive device array structure with a value that is programmable during manufacturing. The device structure includes a substantially conductive first layer having a plurality of passive device array elements of the integrated passive device ... | 08/28/2001 |
| 6114713 | Integrated circuit memory cell having a small active area and method of forming same A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a s... | 09/05/2000 |
| 6107666 | High density ROM and a method of making the same The method includes forming a first insulating layer over a substrate. A first metal layer is formed over the first insulating layer. The first metal layer is patterned to form a plurality of parallel bit lines. A second insulating layer is formed over th... | 08/22/2000 |
| 6015977 | Integrated circuit memory cell having a small active area and method of forming same A method for manufacturing a memory device having a plurality of memory cells. Each memory cell has a non-volatile resistive memory element with a small active area. A plurality of memory cells are formed at selected locations of at least a portion of a s... | 01/18/2000 |
| 5998275 | Method for programmable integrated passive devices A method for endowing an integrated passive device array structure with a programmable value during manufacturing. The method includes forming a substantially conductive first layer and forming a plurality of passive device array elements of the integrate... | 12/07/1999 |
| 5973633 | Weighted capacitor array with selective grouping to form array elements An integrated circuit for analog to digital conversion using a plurality of unit capacitors (201). The value of each unit capacitor (201) has a nonlinear spatial component determined by the location of the unit capacitor (201) on the integrated circuit. A... | 10/26/1999 |
| 5840608 | High density ROM and a method of making the same The method includes forming a first insulating layer over a substrate. A first metal layer is formed over the first insulating layer. The first metal layer is patterned to form a plurality of parallel bit lines. A second insulating layer is formed over th... | 11/24/1998 |
