Class 257/E27.067 - Including both N- and P- wells in the substrate, e.g. twin-tub (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 258
Last issue date: 08/12/2008

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Number	Title	Issue Date
7410855	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f...	08/12/2008
7411253	CMOS transistors using gate electrodes to increase channel mobilities by inducing localized channel stress A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second re...	08/12/2008
7391083	Semiconductor device and a method of manufacturing the same A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger...	06/24/2008
7391085	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f...	06/24/2008
7372104	High voltage CMOS devices A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that...	05/13/2008
7365377	Semiconductor integrated circuit device using four-terminal transistors In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed i...	04/29/2008
7323349	Self-aligned cross point resistor memory array A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the...	01/29/2008
7271449	Semiconductor device having triple-well structure A semiconductor device has a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type which is formed to extend from the surface of the semiconductor substrate toward the inside thereof, a pair of second well regions o...	09/18/2007
7268400	Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin...	09/11/2007
7256462	Semiconductor device The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region....	08/14/2007
7199422	Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and operation Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for ea...	04/03/2007
7101763	Low capacitance junction-isolation for bulk FinFET technology The present invention provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capaci...	09/05/2006
6969901	Method and structure for a low voltage CMOS integrated circuit incorporating higher-voltage devices A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (	11/29/2005
6636075	Semiconductor integrated circuit and its fabrication method An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type...	10/21/2003
6630710	Elevated channel MOSFET The present invention provides a semiconductor device (e.g., MOSFET) having a channel above the surface of the wafer containing a well and a junction. The elevated channel may be selectively epitaxially grown and enables higher mobility, thereby enabling ...	10/07/2003
6621327	Substrate voltage selection circuit Transistors are supplied with either a first power supply voltage or a second power supply voltage lower than the first power supply voltage. During an operation period of the transistors, substrate voltages of the transistors are set at a value between t...	09/16/2003
6621325	Structures and methods for selectively applying a well bias to portions of a programmable device Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integr...	09/16/2003
6605857	Reducing magnetic coupling using triple well An integrated inductive element may be formed over a substrate. A triple well may be defined in a star-shape, in one embodiment, in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic couplin...	08/12/2003
6600360	Semiconductor integrated circuit In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to incl...	07/29/2003
6593799	Circuit including forward body bias from supply voltage and ground nodes One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transisto...	07/15/2003
6583473	Semiconductor devices containing surface channel mos transistors An intermediate semiconductor device for use in making surface channel MOS transistors is disclosed. The intermediate semiconductor device includes a semiconductor substrate having a top surface, a bottom surface, a plurality of doped isolation regions an...	06/24/2003
6576966	Field-effect transistor having multi-part channel An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transisto...	06/10/2003
6573577	Semiconductor device and method for fabricating the same A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the d...	06/03/2003
6542043	All PMOS fully differential voltage controlled oscillator All PMOS (p channel metal oxide semiconductor) fully differential voltage controlled oscillator (VCO). A fully differential implementation within the present invention provides for a very effective rejection of common mode noises. In addition, the PMOS im...	04/01/2003
6535034	High performance integrated circuit devices adaptable to use lower supply voltages with smaller device geometries A high performance integrated circuit device enables scaled low voltage transistors to be utilized as transfer gates with improved speed characteristics. At least some of the transistors are formed with thicker gate oxides and boosted positive and negativ...	03/18/2003
6483374	Semiconductor integrated circuit In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to incl...	11/19/2002
6475887	Method of manufacturing semiconductor device A semiconductor device which can effectively prevent impurity diffusion in heat treatment for electrically activating the impurity, and a manufacturing method thereof are disclosed. In the semiconductor device, a diffusion preventing layer having a depth ...	11/05/2002
6455915	Integrated inductive circuits An integrated inductive element may be formed over a substrate. A trench may be defined in a variety of shapes in the substrate beneath the integrated inductive element in order to reduce eddy current losses arising from magnetic coupling between integrat...	09/24/2002
6451640	Semiconductor device having NMOS and PMOS transistors on common substrate and method of fabricating the same There is provided a method of fabricating a semiconductor device, including the steps of (a) forming first well regions in a semiconductor substrate in all regions in which high-voltage and low-voltage MOS transistors are to be formed, the semiconductor A...	09/17/2002
6441442	Integrated inductive circuits An RF circuit may be formed over a triple well that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substra...	08/27/2002
6426673	High performance integrated radio frequency circuit devices A radio frequency device may be formed which has high power output and high transistor switching speeds. This may be done by providing thicker gate oxides and a higher supply potential to transistors utilized to form the power amplifier and using thinner ...	07/30/2002
6423589	Methods for fabricating CMOS integrated circuits including source/drain compensating regions A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is locat...	07/23/2002
6413808	Semiconductor device and process for production thereof In the semiconductor device disclosed in the present invention, the well regions in the internal circuit comprise high-impurity-concentration regions 4 and 5 as lower layers and low-impurity-concentration regions 2 and 3 as upper layers, and the well regi...	07/02/2002
6411156	Employing transistor body bias in controlling chip parameters In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in t...	06/25/2002
6388498	Semiconductor device capable of reducing noise A signal is transmitted to/from an analog circuit portion and a digital circuit portion through an interface circuit portion. Analog circuit portion, digital circuit portion and interface circuit portion are externally supplied with power from different p...	05/14/2002
6380015	MOSFETs with improved short channel effects and method of making the same In the manufacture of CMOS devices, the n+ gate is partially counterdoped with boron to produce a modified p-type FET that has improved short channel effects, reduced gate induced drain leakage and gate oxide fields for improved reliability. A doped polys...	04/30/2002
6359472	Semiconductor integrated circuit and its fabrication method An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type...	03/19/2002
6342719	Semiconductor device having a double-well structure and method for manufacturing the same A first well of the same conductivity type as that of a semiconductor substrate and a second well of a conductivity type opposite to that of the semiconductor substrate, are formed in the semiconductor substrate. The second well isolates the semiconductor...	01/29/2002
6337593	Semiconductor integrated circuit In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to incl...	01/08/2002
6326254	Method of manufacturing semiconductor device Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors h...	12/04/2001

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Class 257/E27.067 - Including both N- and P- wells in the substrate, e.g. twin-tub (EPO)