Class 257/E27.066 - Including a P-well only in the substrate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 66
Last issue date: 04/08/2008

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Number	Title	Issue Date
7355218	Semiconductor component with a MOS transistor The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as t...	04/08/2008
7317223	Memory device and method of manufacturing the same In one embodiment, a memory device includes a semiconductor substrate, a first region formed in a predetermined region of the semiconductor substrate, and in which a plurality of memory transistors are disposed, and a second region adjacent to the first region, and ...	01/08/2008
6583470	Radiation tolerant back biased CMOS VLSI A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be ...	06/24/2003
6451676	Method for setting the threshold voltage of a MOS transistor A method for setting the threshold voltage of a MOS transistor having a gate composed of polysilicon includes the step of implanting germanium ions into the gate composed of polysilicon in order to change the work function of the gate....	09/17/2002
6171895	Fabrication of buried channel devices with shallow junction depth The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation o...	01/09/2001
6160295	CMOS device A CMOS arrangement is described which has at least one NMOS region (2) and at least one PMOS region (3) and which is provided at its surface with substrate contacts (24, 34), via which it is possible to apply predetermined voltage values to respective sub...	12/12/2000
5894155	Metal gate high voltage integrated circuit/process A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided. The method comprises forming a first mask...	04/13/1999
5864163	Fabrication of buried channel devices with shallow junction depth The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation o...	01/26/1999
5624858	Method of manufacturing a semiconductor device with increased breakdown voltage A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration im...	04/29/1997
5610435	Semiconductor device having an electrode which controls a surface state of the base area for minimizing a change of the D.C. amplification ratio A bipolar transistor having a control electrode area of a semiconductor of a first conductive type, and first and second main electrode areas positioned in contact with the control electrode area and composed of a semiconductor of a second conductive type...	03/11/1997
5498553	Method of making a metal gate high voltage integrated circuit A semiconductor is made on a silicon substrate containing an impurity of a predetermined polarity having formed therein a well containing an impurity of an opposite polarity to a region in the silicon is provided. The method comprises forming a first mask...	03/12/1996
5495124	Semiconductor device with increased breakdown voltage A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration im...	02/27/1996
5446689	Semiconductor memory having a polycrystalline silicon load resistor and CMOS peripheral circuitry A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline si...	08/29/1995
5420062	Method of manufacturing an insulated gate FET having double-layered wells of low and high impurity concentrations This invention relates to an insulated gate FET in which the withstanding voltage and the latch-up resistant property are both made high. The structure thereof includes a second well formed in a first well and having an impurity concentration lower than t...	05/30/1995
5382820	High voltage CMOS device to integrate low voltage controlling device A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first mask...	01/17/1995
5359562	Semiconductor memory having polycrystalline silicon load resistors and CMOS peripheral circuitry A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline si...	10/25/1994
5342803	Method for isolating circuit elements for semiconductor device Provided is a method for isolating circuit elements for effectively isolating devices on a semiconductor substrate from each other with use of a narrow insulating film. With such a method there is no likelihood of causing crystal defect in the semiconduct...	08/30/1994
5317175	CMOS device with perpendicular channel current directions P channel MOSFET and N channel MOSFET are formed in a (011) orientated semiconductor surface in such a manner that the channel of the P channel MOSFET is perpendicular to the channel of the N channel MOSFET. This arrangement can reduce a total channel res...	05/31/1994
5268323	Semiconductor array and method for its manufacture A semiconductor array in a CMOS technology is described in which the gate electrodes are of p+ -doped polysilicon in the case of p-channel transistors and of n+ -doped polysilicon in the case of n-channel transistors. If the gate ele...	12/07/1993
5260594	Semiconductor device reducing internal noises and integrated circuit employing the same A semiconductor device of the present invention capable of obtaining a proper output signal by absorbing an overshoot or an undershoot to reduce internal noises, comprises, a logical circuit portion including a transistor, a first diode disposed between a...	11/09/1993
5220191	Semiconductor device having a well electrically insulated from the substrate The semiconductor device comprises a semiconductor substrate 11; a semiconductor layer 12 different in conductivity type from and lower in oxygen concentration than the semiconductor substrate, and formed uniformly on the substrate; a well region 13 diffe...	06/15/1993
5124763	Insulated-gate type integrated circuit A P-well region is provided in a semiconductor substrate of N-type. A P-channel MOSFET is arranged in the N-type substrate while an N-channel MOSFET is arranged in the P-well region. The drain regions of the respective MOSFETs consist of high concentratio...	06/23/1992
5115297	Complementary type semiconductor integrated circuit device A complementary type semiconductor integrated circuit device includes a semiconductor substrate of a first conductivity type connected to a high potential input terminal, a first well region and a second well region, both of a second conductivity type and...	05/19/1992
5083179	CMOS semiconductor integrated circuit device In a CMOS semiconductor integrated circuit device, an element isolating insulation film is formed on an N-type epitaxial layer deposited on an N-type semiconductor substrate, and two CMOS circuits are arranged in a region surrounded by the element isolati...	01/21/1992
5028556	Process for fabricating radiation hard high voltage devices A radiation hard, high voltage integrated circuit device fabrication process. A silicon substrate is implanted with ions that form a buried layer and an epitaxial layer of silicon is grown thereover. The structure is heated to form adjacent N- and P-chann...	07/02/1991
4954871	Semiconductor device with composite electrode Provided is a semiconductor device having a single continuous wiring layer in which a predetermined portion thereof is made of a semiconductor material, and the remaining portion thereof is made of a metal compound of the semiconductor material. The prede...	09/04/1990
4920066	Process for fabricating a high-speed CMOS TTL semiconductor device A process for fabricating a high-speed CMOS TTL semiconductor device, wherein the operational speed of a semiconductor device is controlled by adjusting the capacitance of its field region. The capacitance of the field region is adjusted by the thickness ...	04/24/1990
4920399	Conductance-modulated integrated transistor structure Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, a...	04/24/1990
4872045	Input protection device for C-MOS device An input protection device for a C-MOS device having an n-type semiconductor substrate and a p-type well region. The device comprises a diode consisting of the p-type well region and an n+ -type layer diffusion formed in the p-type well region ...	10/03/1989
4866002	Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof In a complementary insulated-gate field effect transistor including insulated-gate field effect transistors of p-channel and n-channel types, a portion of the insulating material layer to be used to form the n-channel transistor is formed to be thicker th...	09/12/1989
4857986	Short channel CMOS on 110 crystal plane A monocrystalline silicon substrate having a (110) crystal plane is prepared. A CMOS transistor is formed on this substrate. An N channel MOS transistor and a P channel MOS transistor are formed in the surface of the semiconductor substrate. In each of th...	08/15/1989
4829359	CMOS device having reduced spacing between N and P channel The separation constraint between the respective junctions formed between the drain regions of the complementary transistors and the semiconductor material in which they are formed is obviated by a structure which permits the respective drain regions of t...	05/09/1989
4827325	Protective optical coating and method for use thereof A multilayer optical coating for semiconductor substrates characterized in that it is etchable by conventional techniques used for fabrication of integrated circuits and has high reflectivity....	05/02/1989
4812889	Semiconductor device FET with reduced energy level degeneration A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first impurity region of second conductivity which is formed in the substrate, a second impurity region of the second conductivity type which is formed in the subst...	03/14/1989
4769686	Semiconductor device Herein disclosed is a semiconductor device, especially, an MISFET which can ensure a high breakdown voltage and operate at a high speed. The semiconductor device according to the present invention reduces the sheet resistance by using an impurity region, ...	09/06/1988
4670672	C-MOS logic circuit supplied with narrow width pulses converted from input pulses A logic circuit comprises an input terminal receiving an input signal of input pulses; first and second stages of C-MOS circuit formed by a first MOS FET of one channel type formed in said semiconductor substrate of one conductivity type and a second MOS ...	06/02/1987
4549198	Semiconductor device A semiconductor device comprises a semiconductor substrate of N conductivity, a semiconductor well of P conductivity type, a first semiconductor region of P conductivity type formed in the substrate, the first semiconductor region forming a source region ...	10/22/1985
4533932	Semiconductor device with enlarged corners to provide enhanced punch through protection A method is provided by the present invention for manufacturing a semiconductor device which includes supplying an impurity for forming an impurity area in a semiconductor substrate wherein the amount of the impurity defining the corners of said area is a...	08/06/1985
4523216	CMOS device with high density wiring layout A CMOS device has P- and N-channel transistors sandwiching an isolation region formed on a semiconductor substrate. The drain regions, as well as the gate regions, of both transistors are connected by respective wiring layers made of polycrystalline silic...	06/11/1985
4458262	CMOS Device with ion-implanted channel-stop region and fabrication method therefor Integrated MOS devices with intermediate ion-implanted regions for minimizing device interaction. Several configurations are detailed; they are individually or, in combination, extremely useful in maximizing the density of ROM functions implemented in the...	07/03/1984

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Class 257/E27.066 - Including a P-well only in the substrate (EPO)