Class 257/E27.065 - Including an N-well only in the substrate (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 53
Last issue date: 04/08/2008

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Number	Title	Issue Date
7355218	Semiconductor component with a MOS transistor The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as t...	04/08/2008
7285453	Triple well structure and method for manufacturing the same The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first con...	10/23/2007
7122867	Triple well structure and method for manufacturing the same The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first con...	10/17/2006
6630375	Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same c...	10/07/2003
6492688	Dual work function CMOS device A method for forming a CMOS device. The method includes forming a gate oxide over a surface of a semiconductor substrate. A first doped layer is formed over the gate oxide. The first doped layer is lithographically patterned comprising selectively removin...	12/10/2002
6414360	Method of programmability and an architecture for cold sparing of CMOS arrays A P-channel transistor is disclosed having P+ source and drain regions formed in a N- well, which is formed in a P- substrate. A third P+ region is provided that functions as a well tie. When the P-channel transistor is used as the pull-up transistor in a...	07/02/2002
6368905	Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same c...	04/09/2002
6255700	CMOS semiconductor device A semiconductor device comprises a depletion-type NMOS transistor having a source region, a drain region connected to a power supply line, and a gate electrode connected to a ground line. An enhancement-type NMOS transistor has a source connected to the g...	07/03/2001
6144080	Semiconductor integrated circuit device having field shield MOS devices A semiconductor integrated circuit has P-channel active MOSFETs and N-channel active MOSFETs formed in a semiconductor substrate. In order to electrically isolate the active MOSFETs, the semiconductor integrated circuit has P-channel field shield MOS devi...	11/07/2000
6107128	Semiconductor device and method of manufacturing the same Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided i...	08/22/2000
6043114	Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same c...	03/28/2000
6010925	Method of making dual-gate CMOSFET A method of making dual-gate structure with only three masking steps is provided. The process comprising: forming well and isolation region to define PMOS and NMOS regions on a semiconductor substrate; forming a conformal layer of PMOS gate oxide by therm...	01/04/2000
5893733	Method of forming an electrostatic-discharge protecting circuit An electrostatic-discharge (ESD) protecting circuit of a semiconductor device prevents damage from an ESD applied to an internal circuit through an input or output pad. The thickness of respective gate insulating layers of respective active devices of the...	04/13/1999
5883423	Decoupling capacitor for integrated circuit signal driver A decoupling capacitor for an integrated circuit and method of forming the same. The decoupling capacitor includes a p-channel device having first and second p-type doped diffusion regions, a device channel region therebetween, a device gate overlying the...	03/16/1999
5883415	CMOS semiconductor device with improved layout of transistors near LCD drive terminals An improved layout of transistors near LCD drive terminals in a CMOS semiconductor device to reduce a chip size without damaging resistances against electrostatic destruction and latch-up. MOSFETs whose sources are connected to neither an electric source ...	03/16/1999
5821146	Method of fabricating FET or CMOS transistors using MeV implantation A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after...	10/13/1998
5818087	Electrostatic-discharge protecting circuit and method An electrostatic-discharge (ESD) protecting circuit of a semiconductor device prevents damage from an ESD applied to an internal circuit through an input or output pad. The thickness of respective gate insulating layers of respective active devices of the...	10/06/1998
5751047	Semiconductor circuit with reduced P-N junction capacitance The semiconductor device according to the present invention includes a semiconductor substrate of a first conductive type. A well area of the first conductive type is formed in the substrate. The well area has higher concentration of impurity than that of...	05/12/1998
5744843	CMOS power device and method of construction and layout CMOS power device (10) is provided. A tank region (62) is formed in a semiconductor substrate (60). A polysilicon gate layer (34) is disposed above the tank region (62) and defines a plurality of source and drain diffusion openings (38 and 36) having roun...	04/28/1998
5721170	Method of making a high-voltage MOS transistor with increased breakdown voltage In a high-voltage MOS transistor that utilizes a lightly-doped drain region to isolate a heavily-doped drain region from the substrate, the reverse bias which can be applied across the drain-to-substrate junction of the transistor is increased by reducing...	02/24/1998
5702973	Method for forming epitaxial semiconductor wafer for CMOS integrated circuits The present invention is a CMOS epitaxial semiconductor wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly do...	12/30/1997
5620922	Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon A method for fabricating a semiconductor device having a high-resistance polysilicon and low-resistance polysilicon on the surface of a substrate comprises forming a gate oxide film on the substrate, forming a polysilicon film on the gate oxide film, and ...	04/15/1997
5550064	Method for fabricating high-voltage complementary metal-oxide-semiconductor transistors A method for fabricating high-voltage CMOS transistors comprises the steps of: forming a well of a second conductivity type and two lightly-doped diffusion regions of the second conductivity type in a silicon substrate of a first conductivity type; formin...	08/27/1996
5545577	Method of producing a semiconductor device having two MIS transistor circuits After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation r...	08/13/1996
5506528	High speed off-chip CMOS receiver A CMOS pass gate receiver improves chip-to-chip communication speed for high speed chips. The high speed CMOS pass gate receiver is immune to overshoot or undershoot and can operate in a frequency greater than or equal to 400 Mhz....	04/09/1996
5500548	Non-epitaxial CMOS structures and processors An integrated circuit device (10) is provided that comprises an P-FET (12) and an N-FET (14) formed on a semiconductor substrate (32). The P-FET (12) is formed in an n- tank (46). The source (18) and back-gate contact (22) of the P-FET (12) are connected ...	03/19/1996
5497021	CMOS structure with varying gate oxide thickness and with both different and like conductivity-type gate electrodes After forming a gate oxide film on the surface side of a single crystalline silicon substrate, a first polycrystalline silicon layer is subsequently formed. After that, portions of polycrystalline silicon layers are left in each gate electrode formation r...	03/05/1996
5489794	Semiconductor device The semiconductor device contains a CMOS transistor pair comprised of a P channel MOS transistor having a polysilicon gate 4 and an N channel MOS transistor having a polysilicon gate. The MOS transistor has a channel dope layer 5 localized in a vicinity o...	02/06/1996
5463240	CMIS device with increased gain In a CMIS device having a semiconductor substrate including a first N-type region and a P-type region, a second P-type region is formed within the first N-type region, and a second N-type region is formed within the first P-type region. Also, a third N-ty...	10/31/1995
5453713	Noise-free analog islands in digital integrated circuits An integrated circuit chip has both digital and analog circuit functions, with one or more islands for isolating the analog functions from noise caused by the digital functions. An island is defined by a surrounding heavily-doped region in the face of the...	09/26/1995
5391904	Semiconductor delay circuit device A semiconductor delay circuit device comprises a pair of transistors of the same conduction type having source regions that are arranged adjacent to each other and facing each other, and a substrate contact diffusion region whose conduction type is opposi...	02/21/1995
5336637	Silicide interconnection with Schottky barrier diode isolation In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect...	08/09/1994
5321293	Integrated device having MOS transistors which enable positive and negative voltage swings A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. This invention is based on elimination of the elect...	06/14/1994
5312767	MOS type field effect transistor and manufacturing method thereof A MOS type field effect transistor includes a columnar insulation layer (22) formed in a concave portion of semiconductor layer (23) that is formed on a main surface of a semiconductor substrate (21). One source drain region (15) is formed annularly in th...	05/17/1994
5306939	Epitaxial silicon wafers for CMOS integrated circuits The present invention is a CMOS epitaxial silicon wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped mo...	04/26/1994
5290725	Semiconductor memory device and a method for producing the same A method for producing a semiconductor memory device including a volatile memory element, a non-volatile memory element, and a driver in combination on a silicon conductive substrate is provided. The volatile memory element is a DRAM and is disposed in an...	03/01/1994
5286667	Modified and robust self-aligning contact process The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silico...	02/15/1994
5250834	Silicide interconnection with schottky barrier diode isolation In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect...	10/05/1993
5225701	Vertical silicon-on-insulator (SOI) MOS type field effect transistor A MOS type field effect transistor includes a columnar insulation layer (22) formed in a concave portion of semiconductor layer (23) that is formed on a main surface of a semiconductor substrate (21). A first source or drain area (25) is formed annularly ...	07/06/1993
5181090	High voltage CMOS devices A semiconductor memory and method of manufacture which are particularly useful for a high breakdown voltage EEPROM wherein high breakdown voltage transistors which are employed in a relatively large number and therefore greatly affect the integration dens...	01/19/1993

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Class 257/E27.065 - Including an N-well only in the substrate (EPO)