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| Number | Title | Issue Date |
| 7442996 | Structure and method for enhanced triple well latchup robustness Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues betwe... | 10/28/2008 |
| 7396732 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille... | 07/08/2008 |
| 7358573 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 04/15/2008 |
| 7342281 | Electrostatic discharge protection circuit using triple welled silicon controlled rectifier Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well cor... | 03/11/2008 |
| 7309883 | Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, an... | 12/18/2007 |
| 7268400 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 09/11/2007 |
| 7244992 | Turn-on-efficient bipolar structures with deep N-well for on-chip ESD protection A semiconductor device suitable for applications in an electrostatic discharge (ESD) protection circuit, including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, and a first doped region formed in the second w... | 07/17/2007 |
| 6686252 | Method and structure to reduce CMOS inter-well leakage A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligne... | 02/03/2004 |
| 6683362 | Metal-semiconductor diode clamped complementary field effect transistor integrated circuits The subject invention relates to a metal-semiconductor diode clamped semiconductor device and method for producing such device. A specific embodiment of the subject invention utilizes one or more Schottky barriers at, for example, the drain and/or source ... | 01/27/2004 |
| 6667522 | Silicon wafers for CMOS and other integrated circuits Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer and forming at least one electrical circuit element in the near-surface region. Integrated circui... | 12/23/2003 |
| 6653708 | Complementary metal oxide semiconductor with improved single event performance A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the f... | 11/25/2003 |
| 6642583 | CMOS device with trench structure A semiconductor device is provided having a high voltage driver IC reducing malfunction or device destruction. A high voltage IC chip includes a trench structure that surrounds each of two semiconductor regions at different electrical potentials. Specific... | 11/04/2003 |
| 6636075 | Semiconductor integrated circuit and its fabrication method An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type... | 10/21/2003 |
| 6617217 | Reduction in well implant channeling and resulting latchup characteristics in shallow trench isolation by implanting wells through nitride Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, a... | 09/09/2003 |
| 6614078 | Highly latchup-immune CMOS I/O structures CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n... | 09/02/2003 |
| 6605872 | Method for fabricating a semiconductor device including a latch-up preventing conductive layer Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the condu... | 08/12/2003 |
| 6593174 | Field effect transistor having dielectrically isolated sources and drains and method for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond... | 07/15/2003 |
| 6583470 | Radiation tolerant back biased CMOS VLSI A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be ... | 06/24/2003 |
| 6493275 | Semiconductor integrated circuit device and electronic equipment Each inverter includes any of a P-channel modulation MOS transistor, a normal N-channel MOS transistor, a normal P-channel MOS transistor, and an N-channel modulation MOS transistor. A modulation substrate bias Vb of the P-channel modulation MOS transisto... | 12/10/2002 |
| 6489657 | Semiconductor device with improved channel stopper A semiconductor device comprising a high withstand voltage MOS transistor of an offset drain/offset source structure easing a high electric field generated between a channel and a parasitic channel stopper in an operating state and preventing changes of a... | 12/03/2002 |
| 6469365 | Semiconductor component with a structure for avoiding parallel-path currents and method for fabricating a semiconductor component A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more hig... | 10/22/2002 |
| 6468848 | Method of fabricating electrically isolated double gated transistor A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diod... | 10/22/2002 |
| 6465283 | Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR wh... | 10/15/2002 |
| 6461904 | Structure and method for making a notched transistor with spacers A method of forming a semiconductor structure includes filling a trench in a first dielectric layer with a gate material. The first dielectric layer is on a semiconductor substrate, and spacers are in the trench. A semiconductor device formed from this st... | 10/08/2002 |
| 6455363 | System to improve ser immunity and punchthrough A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the... | 09/24/2002 |
| 6445044 | Apparatus improving latchup immunity in a dual-polysilicon gate The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps... | 09/03/2002 |
| 6420764 | Field effect transitor having dielectrically isolated sources and drains and methods for making same A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semicond... | 07/16/2002 |
| 6420221 | Method of manufacturing a highly latchup-immune CMOS I/O structure CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n... | 07/16/2002 |
| 6410378 | Method of fabrication of semiconductor structures by ion implantation The present invention relates to formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. P-type dopant are implanted into a semiconductor substrate hav... | 06/25/2002 |
| 6406974 | Method of forming triple N well utilizing phosphorus and boron ion implantations A method of forming a triple N well is described. A first pattern mask layer is formed on a substrate. A first ion implantation step is performed to form an annular longitudinal deep N well in the substrate. A second ion implantation step is performed to ... | 06/18/2002 |
| 6359316 | Method and apparatus to prevent latch-up in CMOS devices A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, wi... | 03/19/2002 |
| 6359472 | Semiconductor integrated circuit and its fabrication method An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type... | 03/19/2002 |
| 6351014 | Semiconductor device having different field oxide sizes According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS activ... | 02/26/2002 |
| 6348372 | Method for reducing PN junction leakage To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus re... | 02/19/2002 |
| 6309940 | Latch-up resistant CMOS structure Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the... | 10/30/2001 |
| 6307233 | Electrically isolated double gated transistor A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diod... | 10/23/2001 |
| 6303964 | Circuit device for protection against electrostatic discharge, immune to the latch-up phenomenon The present invention relates to a circuit device for protection against electrostatic discharge, and being immune to the latch-up phenomenon. The circuit device is of the integrated type in a portion of a semiconductor integrated circuit. The device incl... | 10/16/2001 |
| 6300209 | Method of fabricating triple well of semiconductor device using SEG There is disclosed a triple well of a semiconductor device using SEG and method of forming the same. The method of forming a triple well of a semiconductor device using SEG according to the present invention is characterized in that it comprises the steps... | 10/09/2001 |
| 6291323 | Method of fabrication of semiconductor structures by ion implantation The present invention relates to the formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. Ions of a P-type dopant are implanted into a semiconductor... | 09/18/2001 |
| 6274416 | Method for fabricating a semiconductor device including a latch-up preventing conductive layer Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the condu... | 08/14/2001 |
