Class 257/E27.062 - Complementary MIS (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 422
Last issue date: 10/28/2008

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Number	Title	Issue Date
7442601	Stress enhanced CMOS circuits and methods for their fabrication A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS tr...	10/28/2008
7442960	TFT, method of manufacturing the TFT, flat panel display having the TFT, and method of manufacturing the flat panel display A thin film transistor (TFT) including a semiconductor film that may be simply patterned, a method of manufacturing the TFT, a flat panel display (FPD) including the TFT, and a method of manufacturing the FPD. The TFT includes a gate electrode, source and drain elec...	10/28/2008
7436036	PMOS transistor of semiconductor device, semiconductor device comprising the same, and method for manufacturing the same A PMOS transistor of a semiconductor device exhibiting improved characteristics, a semiconductor device incorporating the same, and a method for manufacturing the semiconductor device. The PMOS transistor incorporates a first gate insulation film formed in a predete...	10/14/2008
7429770	Semiconductor device and manufacturing method thereof A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a ...	09/30/2008
7423330	Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab...	09/09/2008
7420254	Semiconductor device having a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming an impurity containing metal layer on the dielectric layer. A metal gate electrode is then formed from the impurity containing metal...	09/02/2008
7414293	Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel f...	08/19/2008
7408210	Solid state image pickup device and camera An object of the present invention is to simultaneously realize the enlargement of a dynamic range and the downsizing of a pixel. An additional capacitor CS is composed by using: a first capacitor formed of a first diffusion layer, a second diffusion layer and a P w...	08/05/2008
7391085	Semiconductor device A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected f...	06/24/2008
7385256	Transistor arrangement in monocrystalline substrate having stress exerting insulators In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas, and which stress them accordingly, are provided in the semicon...	06/10/2008
7385257	Hybrid orientation SOI substrates, and method for forming the same The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor su...	06/10/2008
7372108	Semiconductor device and manufacturing method thereof The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first se...	05/13/2008
7361540	Method of reducing noise disturbing a signal in an electronic device Certain aspects of a method for reducing noise disturbing at least one signal in an electronic device may comprise shielding a first layer doped with a first dopant from a signaling layer employing a second layer doped with a second dopant. A first signaling compone...	04/22/2008
7348635	Device having enhanced stress state and related methods The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in t...	03/25/2008
7348611	Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a ...	03/25/2008
7345329	Method for reduced N+ diffusion in strained Si on SiGe substrate The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N typ...	03/18/2008
7335911	Semiconductor device and manufacturing method thereof By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce po...	02/26/2008
7317229	Gate electrode structures and methods of manufacture Gate electrode structures used in field effect transistors and integrated circuits and methods of manufacture are disclosed. Improved work function and threshold modulation are provided by the methods and structures. ...	01/08/2008
7285831	CMOS device with improved performance and method of fabricating the same A complementary metal oxide semiconductor (CMOS) device having improved performance includes a first device active region including at least one pair of transistor active regions wherein one transistor active region has a first width and the other transistor active ...	10/23/2007
7271442	Transistor structure having stressed regions of opposite types underlying channel and source/drain regions An integrated circuit and method of fabrication are provided in which the integrated circuit includes a field effect transistor (FET) having a channel region and source and drain regions adjacent to the channel region. A first stressed region having a first type of ...	09/18/2007
7271450	Dual-gate structure and method of fabricating integrated circuits having dual-gate structures A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate struct...	09/18/2007
7224006	Semiconductor device A semiconductor device includes: a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities; an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and a shared line which con...	05/29/2007
7211869	Increasing carrier mobility in NFET and PFET transistors on a common wafer Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partial...	05/01/2007
7160786	Silicon on insulator device and layout method of the same A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped reg...	01/09/2007
7105891	Gate structure and method CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates. ...	09/12/2006
7098511	ESD protection circuit The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the...	08/29/2006
7087969	Complementary field effect transistor and its manufacturing method A complementary field effect transistor comprises: a semiconductor substrate; an n-type field effect transistor provided on the semiconductor substrate; and a p-type field effect transistor provided on the semiconductor substrate. The n-type field effect transistor ...	08/08/2006
6703667	Semiconductor integrated circuit device with connections formed using a conductor embedded in a contact hole The metal layers embedded into the contact holes of various kinds in shape are used as the lines and are employed as the lines for controlling the substrate bias. The first-layer metal line layers are made thin so as to be also employed as the lines for c...	03/09/2004
6703688	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	03/09/2004
6690075	Semiconductor device with channel having plural impurity regions In a CMOS circuit, impurity regions are formed in the channel forming region of each of an n-channel and p-channel transistors alone the channel direction. The intervals between the impurity regions in the n-channel transistor is set narrower than those b...	02/10/2004
6690206	Semiconductor integrated circuit device A pass-transistor logic circuit configuration that can form a high-speed chip in a small area with short wire length. In a selector circuit PMOS and NMOS transistors with different gate signals but with the same drain outputs are arranged, respectively, s...	02/10/2004
6677192	Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic p...	01/13/2004
6674099	MISFET A metal insulator semiconductor field effect transistor (MISFET) is disclosed comprising a source layer being made with a material having a source band-gap (EG2) and a source mid-gap value (EGM2), the source layer having a source Fermi-Level (EF2). A drai...	01/06/2004
6674100	SiGeC-based CMOSFET with separate heterojunctions Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in...	01/06/2004
6664608	Back-biased MOS device A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. T...	12/16/2003
6657285	Semiconductor anti-interference band for integrated circuit A semiconductor anti-interference band distributed on peripheries of partial of regional circuits in an integrated circuit is assembled by an unequal number of PNP structures; two metal bands are disposed on the surface layer of the integrated circuit, wh...	12/02/2003
6653687	Insulated gate semiconductor device Dot-pattern-like impurity regions 104 are artificially and locally formed on a channel forming region 103. The impurity regions 104 restrain the expansion of a drain side depletion layer toward the channel forming region 103 to prevent the short channel e...	11/25/2003
6653709	CMOS output circuit with enhanced ESD protection using drain side implantation A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS ...	11/25/2003
6653693	Semiconductor integrated circuit device A semiconductor integrated circuit device of a low power consumption capable of performing under a low voltage has an array section 21 in which only low threshold voltage MOS FETs are formed, and areas other than the array section 21 in which high thresho...	11/25/2003
6653181	CMOS integrated circuit having vertical transistors and a process for fabricating same A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer...	11/25/2003

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Class 257/E27.062 - Complementary MIS (EPO)