Class 257/E27.061 - Combination of depletion and enhancement field-effect transistors (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 74
Last issue date: 06/05/2007

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Number	Title	Issue Date
7227231	Semiconductor integrated circuit device A semiconductor integrated circuit device has a first MOS transistor and a second MOS transistor. The first MOS transistor has a first source, a first gate electrode, and a first wiring metal connected to the first source and overlapping the first gate electrode. Th...	06/05/2007
7087967	LSI device having core and interface regions with SOI layers of different thickness An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region...	08/08/2006
6703670	Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention ...	03/09/2004
6653694	Reference voltage semiconductor A reference voltage circuit with a small change in output voltage with respect to temperature change has an enhancement mode MOS and a depletion mod MOS, a polarity of a gate of the enhancement mod MOS is opposite that of the transistor, and a polarity of...	11/25/2003
6593191	Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp...	07/15/2003
6555839	Buried channel strained silicon FET using a supply layer created through ion implantation A circuit including at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET. The depletion mode FET includes an ion implanted dopant supply. In exemplary embodiments, the FETs are surface channel or burie...	04/29/2003
6500715	Method of forming a CMOS structure having gate insulation films of different thicknesses The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the ...	12/31/2002
6307236	Semiconductor integrated circuit device The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the ...	10/23/2001
6200838	Compound semiconductor device and method of manufacturing the same In a compound semiconductor device constituting a field effect transistor having a buried p region 3, a channel region 4 is formed thin and highly doped by n-type impurity, and the buried p region 3 is formed shallowly and highly doped by p-type impurity ...	03/13/2001
5923984	Method of making enhancement-mode and depletion-mode IGFETS with different gate materials A method of making enhancement-mode and depletion-mode IGFETs with different gate materials is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a first gate composed of a first gate material ...	07/13/1999
5514610	Method of making an optimized code ion implantation procedure for read only memory devices A process designed to fabricate depletion mode MOSFET devices, for ROM applications, has been developed. A key feature of this fabrication sequence is the ion implantation step used to create the programmable cell. The code implant step is performed throu...	05/07/1996
5382819	Semiconductor device having MOS source follower circuit A semiconductor device having a source follower circuit is configurated in such a way that a first and a second p-type wells are formed by diffusing a p-type impurity into an n-type semiconductor substrate doped with an n-type impurity of a low density. N...	01/17/1995
5371418	Drive circuit for a power MOSFET with load at the source side Power FETs having a load at the source side require a gate voltage lying above the drain voltage in order to be driven completely conductive. This can occur with a known pump circuit. In the drive circuit disclosed, the diode connected to the gate termina...	12/06/1994
5323048	MIS type semiconductor ROM programmed by conductive interconnects An MIS device which includes a source diffusion layer and a drain diffusion layer under the surface of a semiconductor substrate, and a plurality of gate insulation films on the surface of the semiconductor substrate. Further, a plurality of gate electrod...	06/21/1994
5311115	Enhancement-depletion mode cascode current mirror An improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-channel transistor devices...	05/10/1994
5245207	Integrated circuit A depletion operation is realized by using a depletion type MOSFET even at the room temperature or the liquid nitrogen temperature without doping the channel portion below the gate electrode with impurities having a conductivity type, which is opposite to...	09/14/1993
5229633	High voltage lateral enhancement IGFET A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one cond...	07/20/1993
5135880	Method of manufacturing a semiconductor device A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one cond...	08/04/1992
5077586	VDMOS/logic integrated circuit comprising a diode An integrated circuit includes a vertical power transistor, a depletion-mode lateral MOS logic transistor and a lateral Schottky diode in an N+ epitaxial semiconductor layer of an N substrate. The depletion-mode lateral transistor and Schottky...	12/31/1991
5045902	VDMOS/logic integrated circuit comprising a vertical depleted MOS transistor and a zener diode and a method of making same An integrated circuit comprises power elements of the enhanced vertical diffused MOS (VDMOS) transistor type (1) and logic elements of the depleted (2) and enhanced (3) lateral MOS transistor type, and further comprises an internal voltage reference resul...	09/03/1991
5038188	Insulated-gate type transistor and semiconductor integrated circuit using such transistor An insulated-gate type transistor having a semiconductor body of a low impurity concentration, a heavily-doped source region of a conductivity type opposite to that of the semiconductor body for supplying charge carriers, a heavily-doped region for receiv...	08/06/1991
5021356	Method of making MOSFET depletion device A p-channel depletion device in a MOSFET is formed and preferably comprises a silicon substrate, an N-well region, P+ source and drain regions, and a polysilicon gate which has been appropriately doped to be of a P- conductivity type. The resulting struct...	06/04/1991
4994872	Insulated gate static induction transistor and integrated circuit including same An insulated-gate static induction transistor is formed by establishing a potential barrier in a semiconductor region of one conductivity type between the source and the drain regions of the other conductivity type. The height of the potential barrier sho...	02/19/1991
4939571	Insulated-gate type transistor and semiconductor integrated circuit using such transistor An insulated-gate type transistor having a semi-conductor body of a low impurity concentration, a heavily-doped source region of a conductivity type opposite to that of the semiconductor body for supplying charge carriers, a heavily-doped drain region for...	07/03/1990
4814839	Insulated gate static induction transistor and integrated circuit including same An insulated-gate static induction transistor is formed by establishing a potential barrier in a semiconductor region of one conductivity type between the source and the drain regions of the other conductivity type. The height of the potential barrier sho...	03/21/1989
4803530	Semiconductor integrated circuit formed on an insulator substrate A semiconductor integrated circuit formed on an insulator substrate and comprising a drive transistor and a load transistor, in which a threshold voltage of the load transistor is set in the range of -2.8V to -1.0V so as to ensure stable operation without...	02/07/1989
4740714	Enhancement-depletion CMOS circuit with fixed output In a CMOS FET IC element including at least one pair of transistors with connected drains, one an N-channel MOSFET and one a P-channel MOSFET, the N-channel MOSFET having a first threshold voltage controlled by the implantation of an ion, and the P-channe...	04/26/1988
4733283	GaAs semiconductor device A method of manufacturing a GaAS semiconductor device of an E/D construction having a GaAs/AlGaAs heterojunction and utilizing a two-dimensional electron gas, which includes the steps of forming a heterojunction semiconductor substrate and etching a porti...	03/22/1988
4663643	Semiconductor device and process for producing the same The present invention is an improvement in a normally off-type high electron mobility transistor (HEMT) having a first single crystalline semiconductor layer, such as an undoped GaAs layer, and a second single crystalline semiconductor layer, such as an N...	05/05/1987
4644386	Integrated circuit employing insulated gate electrostatic induction transistor An insulated gate electrostatic induction transistor and an integrated circuit employing such an insulating gate electrostatic induction transistor as a drive transistor. A highly resistive channel region is provided on a semiconductor substrate of higher...	02/17/1987
4635343	Method of manufacturing GaAs semiconductor device A method of manufacturing a GaAs semiconductor device of an E/D construction having a GaAs/AlGaAs heterojunction and utilizing two-dimensional electron gas, which includes the steps of forming a heterojunction semiconductor substrate and etching a portion...	01/13/1987
4622570	Semiconductor memory A semiconductor memory device of a one-transistor type is manufactured by using a so-called double-layer technology. The device comprises a buried-channel type transistor having normally-off characteristics and a capacitor having normally-on characteristi...	11/11/1986
4606113	Method of manufacturing metal-semiconductor field effect transistors using orientation dependent etched recesses of different depths Field effect transistors are manufactured using a substrate of compound semiconductor material by defining two gate areas which have their longitudinal dimensions so oriented with respect to the crystal axes of the substrate that the substrate material is...	08/19/1986
4583011	Circuit to prevent pirating of an MOS circuit A method and circuit arrangement are disclosed for foiling an attempt to copy an MOS integrated circuit by implementing in the circuit an additional pseudo MOS device, which from its location in the circuit would appear to a would-be copier to be an enhan...	04/15/1986
4578694	Inverter circuit provided with gate protection An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit. The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the...	03/25/1986
4570237	Microprocessor A microprocessor includes an internal data memory, made up of a plurality of memory cells, each of which includes first and second inverter circuits. In selected memory cells, the logic state of the cell is predetermined upon initiation of the power suppl...	02/11/1986
4554644	Static RAM cell A static RAM cell (11) is constructed utilizing low resistivity positive and negative power supply leads (13,14), thus eliminating the problem of instability of the data stored within the cell. The negative power supply lead is formed of a first layer of ...	11/19/1985
4451744	Monolithic integrated reference voltage source The invention discloses a monolithic integrated reference voltage source consisting of a source-drain series arrangement of a depletion-type n-channel MOSFET connected to the supply potential and of an enhancement-type n-channel MOSFET connected to a refe...	05/29/1984
4417263	Semiconductor device A semiconductor device for generating a constant voltage and comprised of a pair of MOS field effect transistors of the same conductivity type connected in series. A first of the transistors is a depletion type and has a gate connected to its source and i...	11/22/1983
4395646	Logic performing cell for use in array structures A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented i...	07/26/1983

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Class 257/E27.061 - Combination of depletion and enhancement field-effect transistors (EPO)