Quotables
"There is no likelihood man can ever tap the power of the atom."
Robert Millikan, Nobel Prize winner in physics
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7442995 | Semiconductor device and method of manufacturing the same Each of channel regions 2a and 3b is covered by a gate electrode 6 via a gate insulation film 5 and side wall spacers 9 from its top face to both side faces along an x-direction. In other words, there is no insulation... | 10/28/2008 |
| 7422953 | Semiconductor device and method of manufacturing the same There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of si... | 09/09/2008 |
| 7423330 | Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab... | 09/09/2008 |
| 7411252 | Substrate backgate for trigate FET Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated fro... | 08/12/2008 |
| 7408226 | Electronic card with protection against aerial discharge An electronic card includes a card terminal which is exposed on a surface of a card, a semiconductor integrated circuit chip including an insulated-gate field effect transistor, and a protection circuit which is provided between the card terminal and the insulated-g... | 08/05/2008 |
| 7402873 | Semiconductor integrated circuit device having deposited layer for gate insulation A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transist... | 07/22/2008 |
| 7382027 | MOSFET device with low gate contact resistance A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with... | 06/03/2008 |
| 7378712 | Gate stacks A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of... | 05/27/2008 |
| 7355253 | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric fo... | 04/08/2008 |
| 7355221 | Field effect transistor having an asymmetrically stressed channel region A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and th... | 04/08/2008 |
| 7339232 | Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each co... | 03/04/2008 |
| 7332774 | Multiple-gate MOS transistor and a method of manufacturing the same Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is... | 02/19/2008 |
| 7332806 | Thin, thermally enhanced molded package with leadframe having protruding region A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate ... | 02/19/2008 |
| 7268401 | Semiconductor integrated circuit device having deposited layer for gate insulation A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transist... | 09/11/2007 |
| 7253484 | Low-power multiple-channel fully depleted quantum well CMOSFETs A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the upperm... | 08/07/2007 |
| 7230296 | Self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 06/12/2007 |
| 7227234 | Embedded non-volatile memory cell with charge-trapping sidewall spacers An IC includes both “volatile” CMOS transistors (FETs) and embedded non-volatile memory (NVM) cells, both including polysilicon gate structures, sidewall oxide layers, sidewall spacer structures, and source/drain regions. The sidewall spacers of both the NVM cel... | 06/05/2007 |
| 7214992 | Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal ... | 05/08/2007 |
| 7208380 | Interface improvement by stress application during oxide growth through use of backside films The present invention provides, in one aspect, a method of fabricating a gate oxide layer on a microelectronics substrate. This embodiment comprises forming a stress inducing pattern on a backside of a microelectronics wafer and growing a gate oxide layer on a front... | 04/24/2007 |
| 7183614 | Semiconductor device and method of manufacture thereof There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by ... | 02/27/2007 |
| 7176090 | Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider... | 02/13/2007 |
| 7138324 | Method of inhibiting degradation of gate oxide film A method of inhibiting degradation of a transistor gate oxide film by high density plasma is disclosed. After a gate electrode is formed, impurity is implanted on the surface of an oxide film, thereby changing surface characteristics of the oxide film to scatter ult... | 11/21/2006 |
| 7112851 | Field effect transistor with electroplated metal gate Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making ... | 09/26/2006 |
| 6822399 | Half-bridge circuit A half-bridge circuit includes: a vertically designed n-conducting first MOS transistor that is integrated in a first semiconductor body having a front side and a rear side; and a vertically designed p-conducting second MOS transistor that is integrated in a second ... | 11/23/2004 |
| 6800916 | Implantable cardiac defibrillation with control circuit for controlling a high voltage circuit using a low voltage circuit Disclosed is an implantable cardiac defibrillator (50) with a circuit comprising a capacitively coupled bridge circuit (10) for using a low-voltage circuit to operate a high-voltage circuit. The invention maintains isolation between the high- and low v... | 10/05/2004 |
| 6700793 | Semiconductor device Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low s... | 03/02/2004 |
| 6696333 | Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes A method of fabricating integrated circuits includes forming MOSFETs with gate electrodes of a first composition, and sidewall spacers along laterally opposed sides of those gate electrodes, removing the gate electrodes of the first composition, and repla... | 02/24/2004 |
| 6693019 | METHOD OF MANUFACTURING AN ELECTRONIC POWER DEVICE MONOLITHICALLY INTEGRATED ON A SEMICONDUCTOR AND COMPRISING A FIRST POWER REGION, A SECOND REGION, AND AN ISOLATION STRUCTURE OF LIMITED PLANAR DIMENSION An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, whi... | 02/17/2004 |
| 6690061 | MOS Semiconductor device The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, th... | 02/10/2004 |
| 6690040 | Vertical replacement-gate junction field-effect transistor A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of differ... | 02/10/2004 |
| 6684378 | Method for designing power supply circuit and semiconductor chip A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor sect... | 01/27/2004 |
| 6683363 | Trench structure for semiconductor devices A MOS trench structure integrated with a semiconductor device for enhancing the breakdown characteristics of the semiconductor device, comprises a semiconductor substrate, a plurality of parallel trenches formed in the semiconductor substrate, a periphera... | 01/27/2004 |
| 6683351 | Semiconductor device having structures that can avoid deterioration caused by the manufacturing processing A semiconductor device restricting the antenna effect without complicating the manufacturing process and a manufacturing method of such a semiconductor device are provided. In addition, a semiconductor device ensuring matching or equality in characteristi... | 01/27/2004 |
| 6680226 | Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the dra... | 01/20/2004 |
| 6680231 | High-voltage device process compatible with low-voltage device process A high-voltage device process compatible with a low-voltage device process. A high-voltage device area and a low-voltage device area are defined on an epitaxial layer of a semiconductor substrate. After forming a plurality of first gate structures on the ... | 01/20/2004 |
| 6656799 | Method for producing FET with source/drain region occupies a reduced area A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide... | 12/02/2003 |
| 6657274 | Apparatus for controlling a high voltage circuit using a low voltage circuit Disclosed is a capacitively coupled bridge circuit for using a low-voltage circuit to operate a high-voltage circuit. The invention maintains isolation between the high- and low-voltage sections by using a capacitor. Also disclosed is the use of the inven... | 12/02/2003 |
| 6649975 | Vertical power devices having trench-based electrodes therein Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and... | 11/18/2003 |
| 6649476 | Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a ... | 11/18/2003 |
| 6642577 | Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same First and second trenches are formed on an n+ type substrate at a power MOSFET formation region and a peripheral device formation region, respectively. An n- type epitaxial film, a p type epitaxial film, and an n+ type epi... | 11/04/2003 |
