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| Number | Title | Issue Date |
| 6373318 | Electronic switching device having at least two semiconductor components An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is als... | 04/16/2002 |
| 6242787 | Semiconductor device and manufacturing method thereof A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-typ... | 06/05/2001 |
| 6157049 | Electronic device, in particular for switching electric currents, for high reverse voltages and with low on-state losses A p-n junction is connected between two terminals. The p-n junction is formed between two semiconductor regions of a semiconductor with a breakdown field strength of at least 106 V/cm. A channel region, which adjoins the p-n junction is connect... | 12/05/2000 |
| 6153453 | JFET transistor manufacturing method The present invention relates to a method of manufacturing a JFET transistor in an integrated circuit containing complementary MOS transistors, this JFET transistor being formed in an N-type well of a P-type substrate, including the steps of forming a P-t... | 11/28/2000 |
| 5989947 | Method for the manufacture of quantum structures, in particular quantum dots and tunnel barriers as well as components with such quantum structures A method of manufacturing quantum structures, in particular quantum dots and tunnel barriers and also a component with such quantum structures wherein in that a substrate is structured by the intentional formation of trenches so that material remains betw... | 11/23/1999 |
| 5973377 | Semiconductor device having FETs with shared source and drain regions The conventional semiconductor device having a switching function is attended with a problem that in addition to a drawback of a large area occupied by the folded structure of gate electrodes, there are not obtained sufficient effect in association with t... | 10/26/1999 |
| 5945699 | Reduce width, differentially doped vertical JFET device A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the we... | 08/31/1999 |
| 5670393 | Method of making combined metal oxide semiconductor and junction field effect transistor device An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between VDD and ground, with a feedback of output voltage to control current from VDD to ground.... | 09/23/1997 |
| 5606184 | Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the ... | 02/25/1997 |
| 5561300 | Atomic switching devices and logical circuits In an atomic switch, opposite ends of an atom wire are connected to an input and output, and a switching gate is connected to a switching power supply. An input signal is outputted when a switching atom is connected to the atom wire, whereas an input sign... | 10/01/1996 |
| 5396085 | Silicon carbide switching device with rectifying-gate A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbid... | 03/07/1995 |
| 5341007 | Semiconductor device and a method for fabricating the same A semiconductor device comprising a plurality of elemental active devices being operable with different threshold voltages is disclosed. Each of the elemental active devices, e.g. D-mode and E-mode HEMT, is formed of each of different active layers epitax... | 08/23/1994 |
| 5313082 | High voltage MOS transistor with a low on-resistance An embodiment of the present invention is an improved insulated-gate, field-effect transistor and a three-sided, junction-gate field-effect transistor connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is ... | 05/17/1994 |
| 5286986 | Semiconductor device having CCD and its peripheral bipolar transistors In a semiconductor device, a charge transfer device, a bipolar transistor, and a MOSFET are formed on a single chip, and the peripheral portion of the charge transfer device is surrounded by an N+ -type region. Since the charge transfer device ... | 02/15/1994 |
| 5241197 | Transistor provided with strained germanium layer A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose ... | 08/31/1993 |
| 5100831 | Method for fabricating semiconductor device A semiconductor device comprising a plurality of elemental active devices being operable with different threshold voltages is disclosed. Each of the elemental active devices, e.g. D made and E made HEMT, is formed of each of different active layers epitax... | 03/31/1992 |
| 5087889 | Area efficient cascode driver circuit A JFET differential amplifier stage in which the gate-drain voltage of each input JFET is kept at least as great as the pinchoff voltage (Vp), but preferably close to Vp so as to reduce the effects of impact ionization and generation... | 02/11/1992 |
| 5060031 | Complementary heterojunction field effect transistor with an anisotype N+ g a -channel devices A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-o... | 10/22/1991 |
| 5005059 | Digital-to-analog converting field effect device and circuitry A field effect device and circuit suitable for providing an analog output signal having a magnitude which is representative of a digital input code having a sequence of bits. The device includes a plurality of gate electrodes located between an input elec... | 04/02/1991 |
| 4811075 | High voltage MOS transistors An insulated-gate, field-effect transistor and a double-sided, junction-gate field-effect transistor are connected in series on the same chip to form a high-voltage MOS transistor. An extended drain region is formed on top of a substrate of opposite condu... | 03/07/1989 |
| 4791072 | Method for making a complementary device containing MODFET Complementary structure implemented in Group III-V compound semiconductors is obtained by using an n-channel field effect transistor and a p-channel MODFET.... | 12/13/1988 |
| 4700213 | Multi-drain enhancement JFET logic (SITL) with complementary MOSFET load A semiconductor integrated logic circuit comprises a load transistor having a carrier injecting region and a carrier extracting region and an inverter transistor having a source region, drain regions, channel regions each connected between the source regi... | 10/13/1987 |
| 4654548 | Complementary logic circuit A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit of the present invention is composed from a first stage comprising a complementary MIS-FET, and an ou... | 03/31/1987 |
| 4612629 | Highly scalable dynamic RAM cell with self-signal amplification A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening t... | 09/16/1986 |
| 4609835 | Semiconductor integrated circuit Disclosed is a semiconductor integrated circuit which comprises an n-type silicon substrate, a p-type well region having an opening at a part thereof, which is formed on the surface portion of the substrate, an MOS transistor formed in the p-type region a... | 09/02/1986 |
| 4546370 | Monolithic integration of logic, control and high voltage interface circuitry Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, a... | 10/08/1985 |
| 4459684 | Nonvolatile JRAM cell using nonvolatile capacitance for information retrieval Non-volatile JRAM cell having interelectrode non-volatile capacitance which is readable and varies with the electrical charge on elements of the device. To program the nonvolatile capacitance, the address lines (word line and bit line) are biased so that ... | 07/10/1984 |
| 4448400 | Highly scalable dynamic RAM cell with self-signal amplification A dynamic RAM memory cell comprises an MOS read transistor whose conductivity state is determined by the state of charge on a first electrode overlying the read transistor channel region. The first electrode is connected through a buried contact opening t... | 05/15/1984 |
| 4449142 | Semiconductor memory device A semiconductor memory device comprises a gate electrode provided via a gate insulating film on a semiconductor layer formed on a substrate and two diffused semiconductor regions provided to form a field effect transistor together with the gate electrode.... | 05/15/1984 |
| 4442448 | Logic integrated circuit device An integrated logic circuit uses thin film IGFET loads integrated with complementary vertical JFET drivers, the IGFETs and JFETs being connected together gate to gate as the input and drain to drain as the effective output node.... | 04/10/1984 |
| 4435785 | Unipolar voltage non-volatile JRAM cell A non-volatile JRAM cell is constructed to require only positive voltage for programming and erasing of data in the cell. The "well" region of the cell JFET device may be implanted with an impurity concentration that will permit lower breakdown voltage or... | 03/06/1984 |
| 4417325 | Highly scaleable dynamic ram cell with self-signal amplification A memory cell comprises a substrate of a first conductivity type (preferably N type) in which is formed a first region of opposite conductivity type. Second, third and fourth regions of first conductivity type are then formed in the first region, said sec... | 11/22/1983 |
| 4409725 | Method of making semiconductor integrated circuit A method of making a semiconductor integrated circuit on a semiconductor substrate containing thereon an SIT and an IG(MOS) FET or an SIT and C-MOS FETs, comprises a series of steps of making these functional semiconductor devices many of which steps are ... | 10/18/1983 |
| 4403395 | Monolithic integration of logic, control and high voltage interface circuitry Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, a... | 09/13/1983 |
| 4402126 | Method for fabrication of a non-volatile JRAM cell A non-volatile memory storage cell utilizing a single vertical junction field-effect transistor is fabricated by a method, which is compatible with the fabrication of MOSFET interface and logic circuits on the same chip. Assembly of a multi-dielectric sta... | 09/06/1983 |
| 4393574 | Method for fabricating integrated circuits A method of fabricating integrated circuits comprises forming a concave portion having bottom and side faces on a semiconductor single-crystal substrate, forming an insulating film on the faces of the concave portion except for at least a portion of the b... | 07/19/1983 |
| 4373253 | Integrated CMOS process with JFET A process for fabricating JFET devices into a conventional CMOS monolithic IC. The combination of devices provides linear circuit operation with low noise characteristics.... | 02/15/1983 |
| 4325180 | Process for monolithic integration of logic, control, and high voltage interface circuitry Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, including various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MO... | 04/20/1982 |
| 4277883 | Integrated circuit manufacturing method A method for forming a semiconductor structure is disclosed wherein a masking layer used to form the gate contact of a Metal Electrode Semiconductor Field Effect Transistor (MESFET) is formed by selectively depositing particles into separated regions of t... | 07/14/1981 |
| 4246498 | Semiconductor integrated driving circuit including C-MOS and junction FET's A semiconductor integrated driving circuit including a junction FET and a C-MOS FET fabricated on a common semiconductor substrate. The junction FET is switched between conductive and non-conductive states for controlling and supplying a high driving curr... | 01/20/1981 |
