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| Number | Title | Issue Date |
| 7436052 | Repatterned integrated circuit chip package A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency. ... | 10/14/2008 |
| 7436031 | Device for implementing an inverter having a reduced size A semiconductor device according to this invention includes: two level shift switches (28A and 28B) each having first and second electrodes, a control electrode, a signal output electrode, and a first semiconductor region forming a transistor device se... | 10/14/2008 |
| 7432143 | Method for forming gate of semiconductor device There is provided a method for forming a gate using a gate layout of a semiconductor device. The layout includes an active region with a stepped side boundary, a plurality of gates crossing over the active region, and tabs attached to the gates on the side boundary ... | 10/07/2008 |
| 7432564 | Pixel structure A method for fabricating a pixel structure is provided. First, a gate, a scan line, and a first terminal are formed on a substrate. A gate insulating layer is formed over the substrate to cover the gate, the scan line, and the first terminal. After defining the semi... | 10/07/2008 |
| 7423308 | Ferroelectric capacitor A ferroelectric capacitor includes a lower electrode, a ferroelectric film provided over the lower electrode and having a perovskite-type structure and an upper electrode provided over the ferroelectric film. The ferroelectric film includes a first ferroelectric fil... | 09/09/2008 |
| 7417302 | Semiconductor device and method of manufacturing the same In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first ... | 08/26/2008 |
| 7414267 | Semiconductor device and process for production thereof Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in... | 08/19/2008 |
| 7407852 | Trench capacitor of a DRAM and fabricating method thereof A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electro... | 08/05/2008 |
| 7400026 | Thin film resistor structure The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conduct... | 07/15/2008 |
| 7381997 | Lateral silicided diodes A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the... | 06/03/2008 |
| 7372092 | Memory cell, device, and system A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The digitline couples with ad... | 05/13/2008 |
| 7362364 | Solid-state image pickup device with photoelectric charge transferrer to a floating diffusion region A solid-state image pickup device including a charge transferrer to transfer a signal charge obtained through photoelectric conversion; a floating diffusion region; a reset means for resetting the potential of the floating diffusion region; and a current source for ... | 04/22/2008 |
| 7358591 | Capacitor device and semiconductor device having the same, and capacitor device manufacturing method In a capacitor device of the present invention, a capacitor parts that has a pair of terminals on both end sides respectively is embedded in an insulating film in a state that a lower surface of the capacitor parts is not covered with the insulating film, then upper... | 04/15/2008 |
| 7358555 | Semiconductor device While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. | 04/15/2008 |
| 7355265 | Semiconductor integrated circuit A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer for... | 04/08/2008 |
| 7348656 | Power semiconductor device with integrated passive component A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof. ... | 03/25/2008 |
| 7348653 | Resistive memory cell, method for forming the same and resistive memory array using the same A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly pa... | 03/25/2008 |
| 7335927 | Lateral silicided diodes A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the... | 02/26/2008 |
| 7335953 | Circuit substrate, electro-optical device, and electronic apparatus The invention provides a circuit substrate including an electrostatic-breakdown-protection circuit efficient for an EL display panel or the like. A substrate includes a common electrode formed on the perimeter of the substrate, multiple terminals formed on the subst... | 02/26/2008 |
| 7335935 | Semiconductor structures Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have... | 02/26/2008 |
| 7332814 | Bondwire utilized for coulomb counting and safety circuits A sense resistor and integrated circuit package combination is disclosed. A package lead frame is provided having a plurality of landing zones associated therewith and a die mounting area for mounting of a die thereon. The die has a plurality of bond pads associated... | 02/19/2008 |
| 7332756 | Damascene gate structure with a resistive device A semiconductor structure having a damascene gate structure and a resistive device on a semiconductor substrate is disclosed. The structure includes a first dielectric layer having a first opening and a second opening formed on the semiconductor substrate, and one o... | 02/19/2008 |
| 7323749 | Semiconductor device comprising an integrated circuit A semiconductor device with a plurality of passive components (7,7a,8,8a) comprising a bottom substrate (1), a buried oxide layer (2) on a portion of the top surface of the bottom substrate (1), an dielectric intermed... | 01/29/2008 |
| 7315054 | Decoupling capacitor density while maintaining control over ACLV regions on a semiconductor integrated circuit In one embodiment, a method of controlling the across-chip line-width variation (ACLV) on a semiconductor integrated circuit includes forming an ACLV controlled region including a plurality of semiconductor devices each having a gate structure and arranging the plur... | 01/01/2008 |
| 7297997 | Semiconductor memory device with dual storage node and fabricating and operating methods thereof A semiconductor memory device with a dual storage node structure as well as methods of fabricating and operating such a device are provided. The semiconductor memory device includes a substrate, a first transistor formed on the substrate, a first storage node connec... | 11/20/2007 |
| 7285827 | Back-to-back NPN/PNP protection diodes A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device. ... | 10/23/2007 |
| 7279753 | Floating base bipolar ESD devices The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits t... | 10/09/2007 |
| 7271454 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 09/18/2007 |
| 7265407 | Capacitive electrode having semiconductor layers with an interface of separated grain boundaries The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxid... | 09/04/2007 |
| 7256498 | Resistance-reduced semiconductor device and methods for fabricating the same Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overli... | 08/14/2007 |
| 7250668 | Integrated circuit including power diode A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fab... | 07/31/2007 |
| 7238981 | Metal-poly integrated capacitor structure A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly silicon layer, a first metal layer and a second metal layer. The first metal layer is positioned between... | 07/03/2007 |
| 7239002 | Integrated circuit device In a temperature sensor section of a semiconductor integrated circuit device, first vias of tungsten are formed at the topmost layer of a multi-layer wiring layer and pads of titanium are provided on regions of the multi-layer wiring layer which covers the vias. An ... | 07/03/2007 |
| 7238994 | Thin film plate phase change ram circuit and manufacturing method A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes elec... | 07/03/2007 |
| 7224012 | Thin film capacitor and fabrication method thereof A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer ins... | 05/29/2007 |
| 7217613 | Low cost fabrication of high resistivity resistors In one disclosed embodiment a layer is formed over a transistor gate and a field oxide region. For example, a polycrystalline silicon layer can be deposited over a PFET gate oxide and a silicon dioxide isolation region on the same chip. The layer is then doped over ... | 05/15/2007 |
| 7202533 | Thin film resistors integrated at a single metal interconnect level of die An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor,... | 04/10/2007 |
| 7169661 | Process of fabricating high resistance CMOS resistor A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional ... | 01/30/2007 |
| 7166507 | Semiconductor device and method for forming same using multi-layered hard mask According to some embodiments of the invention, bit lines are formed using a multi-layered hard mask and BC nodes are separated by forming line-type BCs in the same direction of gate lines. Thus, a narrowing of shoulders between the bit lines and the BCs can be prev... | 01/23/2007 |
| 7161218 | One-time programmable, non-volatile field effect devices and methods of making same One-time programmable, non-volatile field effect devices and methods of making same. Under one embodiment, a one-time-programmable, non-volatile field effect device includes a source, drain and gate with a field-modulatable channel between the source and drain. Each... | 01/09/2007 |
