Class 257/E27.013 - Integrated circuit having a two-dimensional layout of components without a common active region (EPO)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
No. of patents: 19
Last issue date: 10/07/2008

Number	Title	Issue Date
7432549	Di/dt servo power switches The invention relates to a vertical-type power switch disposed in a semi-conductor chip, comprising a winding (30) located on the periphery of at least one face of said chip. Said winding comprises two binding posts (31, 32) which supply a signal that ...	10/07/2008
7385263	Low resistance integrated MOS structure The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are pl...	06/10/2008
7381997	Lateral silicided diodes A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the...	06/03/2008
7335927	Lateral silicided diodes A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the...	02/26/2008
7317223	Memory device and method of manufacturing the same In one embodiment, a memory device includes a semiconductor substrate, a first region formed in a predetermined region of the semiconductor substrate, and in which a plurality of memory transistors are disposed, and a second region adjacent to the first region, and ...	01/08/2008
7307295	Method and an apparatus for a hard-coded bit value changeable in any layer of metal A system including an semiconductor chip with a hard-coded bit changeable in any single metal layer of the semiconductor chip has been presented. In one embodiment, the system includes a graphics chip and an input/output controller hub. The input/output controller h...	12/11/2007
7307294	Circuit layout structure Main-transistors M1 and M2 are divided into sub-transistors that are arrayed in a matrix with four rows and four columns to form four cells so that each of the cells is formed of four of the sub-transistors that have a common center. This can realize a...	12/11/2007
7196392	Semiconductor structure for isolating integrated circuits of various operation voltages A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor...	03/27/2007
7087943	Direct alignment scheme between multiple lithography layers A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor. ...	08/08/2006
6603185	Voltage withstanding structure for a semiconductor device A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends con...	08/05/2003
6495423	Electronic power device monolithically integrated on a semiconductor and comprising edge protection structures having a limited planar dimension An electronic power device is integrated monolithically in a semiconductor substrate. The device includes a power region, itself having at least one P/N junction provided therein which comprises a first semiconductor region with a first type of conductivi...	12/17/2002
6222248	Electronic semiconductor power device with integrated diode A device including an IGBT a formed on a chip of silicon consisting of a P type substrate with an N type epitaxial layer that contains a first P type region and a termination structure, and having a first P type termination region that surrounds the first...	04/24/2001
6191466	Semiconductor device containing a diode A semiconductor device which has few peripheral element malfunctions and superior performance is obtained. The semiconductor device includes a p-type buried layer on a main surface of a semiconductor substrate, an n-type cathode region provided on the p-t...	02/20/2001
5872489	Integrated tunable inductance network and method An integrated, tunable inductance network features a number of fixed inductors fabricated on a common substrate along with a switching network made up of a number of micro-electromechanical (MEM) switches. The switches selectably interconnect the inductor...	02/16/1999
5591658	Method of fabricating integrated circuit chip containing EEPROM and capacitor An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM...	01/07/1997
5569953	Semiconductor device having an isolation region enriched in oxygen A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the...	10/29/1996
5550072	Method of fabrication of integrated circuit chip containing EEPROM and capacitor An EEPROM cell is formed in an IC chip by using only three masking steps in addition to those required for the basic CMOS transistors in the chip. A first mask layer is used to define source/drain regions of select and memory transistors within the EEPROM...	08/27/1996
5480833	Semiconductor device having an isolation region enriched in oxygen and a fabrication process thereof A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the...	01/02/1996
5192701	Method of manufacturing field effect transistors having different threshold voltages A semiconductor device which comprises a semi-insulating substrate and a plurality of field effect transistors (FETs) formed on the semi-insulating substrate. An epitaxial layer of one conductivity type is formed on the semi-insulating substrate by a crys...	03/09/1993

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Class 257/E27.013 - Integrated circuit having a two-dimensional layout of components without a common active region (EPO)