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| Number | Title | Issue Date |
| 7439594 | Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich s... | 10/21/2008 |
| 7427810 | Semiconductor device including semiconductor element mounted on another semiconductor element A semiconductor device including a first semiconductor element mounted on a first surface of second semiconductor element, wherein solder balls are formed on the first surface of the second semiconductor element such that the first surface includes an area without s... | 09/23/2008 |
| 7385283 | Three dimensional integrated circuit and method of making the same A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the ... | 06/10/2008 |
| 7378726 | Stacked packages with interconnecting pins A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die an... | 05/27/2008 |
| 7375420 | Large area transducer array A large area transducer array comprising a substrate having a front side and a backside, a plurality of transducers disposed on the front side of the substrate and patterned in the form of a two-dimensional transducer array in the X-Y plane, a plurality of connector... | 05/20/2008 |
| 7375418 | Interposer stacking system and method The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while t... | 05/20/2008 |
| 7372140 | Memory module with different types of multi chip packages In an embodiment, a memory module includes a first group of multi chip packages, including one or more non-volatile memories, and a second group of multi chip packages, including one or more volatile memories, wherein the first and second groups of multi chip packag... | 05/13/2008 |
| 7355264 | Integrated passive devices with high Q inductors The specification describes flip bonded dual substrate inductors wherein a portion of the inductor is constructed on a base IPD substrate, a mating portion of the inductor is constructed on a cover (second) substrate. The cover substrate is then flip bonded to the b... | 04/08/2008 |
| 7355273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. Th... | 04/08/2008 |
| 7355271 | Flexible assembly of stacked chips A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( | 04/08/2008 |
| 7335974 | Multi stack packaging chip and method of manufacturing the same A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; ... | 02/26/2008 |
| 7332800 | Semiconductor device For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each... | 02/19/2008 |
| 7323774 | Integrated circuit package system with pedestal structure An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of... | 01/29/2008 |
| 7309913 | Stacked semiconductor packages A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semico... | 12/18/2007 |
| 7304375 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 12/04/2007 |
| 7301242 | Programmable system in package Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodi... | 11/27/2007 |
| 7298038 | Integrated circuit package system including die stacking An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die i... | 11/20/2007 |
| 7298037 | Stacked integrated circuit package-in-package system with recessed spacer A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a subs... | 11/20/2007 |
| 7288835 | Integrated circuit package-in-package system An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first inte... | 10/30/2007 |
| 7282791 | Stacked semiconductor device and semiconductor memory module A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless man... | 10/16/2007 |
| 7265441 | Stackable single package and stacked multi-chip assembly A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including co... | 09/04/2007 |
| 7265442 | Stacked package integrated circuit The invention relates to an integrated circuit, electronic device, and method for assembling an integrated circuit package with at least one bottom module with a stacked die package comprising at least two dies within one single mold cap. To allow chip area reductio... | 09/04/2007 |
| 7253530 | Method for producing chip stacks A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact ... | 08/07/2007 |
| 7253512 | Organic dielectric electronic interconnect structures and method for making A method for making a multi-layer electronic structure. A layer of dielectric material having a top surface and a bottom surface is provided. A layer of electrically conducting material is provided on one of the top surface and the bottom surface of the dielectric l... | 08/07/2007 |
| 7247933 | Thin multiple semiconductor die package A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (1... | 07/24/2007 |
| 7235870 | Microelectronic multi-chip module A method of fabricating a microelectronic multi-chip module comprises: providing a cavity down ball grid array having a die and solder balls on a die side thereof; providing a package including at least one die thereon on a die side thereof; stacking the package ont... | 06/26/2007 |
| 7217994 | Stack package for high density integrated circuits A stack package for a high density memory module includes at least one memory chip, an ASIC and an interposer, wherein the interposer comprises a first surface having contacts arranged in electrical communication with corresponding contacts on the ASIC and a second,... | 05/15/2007 |
| 7217993 | Stacked-type semiconductor device A stacked-type semiconductor device includes a first wiring substrate on which a semiconductor device element is mounted, a second wiring substrate stacked on the first wiring substrate through a plurality of electrode terminals which are electrically connected with... | 05/15/2007 |
| 7187068 | Methods and apparatuses for providing stacked-die devices Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and ass... | 03/06/2007 |
| 7157787 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, ... | 01/02/2007 |
| 7126212 | Three dimensional device integration method and integrated device A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after b... | 10/24/2006 |
| 7122912 | Chip and multi-chip semiconductor device using thereof and method for manufacturing same The chip for the multi-chip semiconductor device having the markings for alignment formed on the front surface and/or the back surface of the chip only by the processing from the front surface of the chip (photolithography, etch) and the method for manufacturing sam... | 10/17/2006 |
| 7119425 | Stacked multi-chip semiconductor package improving connection reliability of stacked chips The chip package includes a first and second semiconductor chip. The first semiconductor chip has a first connection structure that electrically connects to a bond pad on a first surface of the first semiconductor chip. The second semiconductor chip has a second con... | 10/10/2006 |
| 7087442 | Process for the formation of a spatial chip arrangement and spatial chip arrangement Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to as... | 08/08/2006 |
| 6677673 | Clamping assembly for high-voltage solid state devices A clamping assembly for use in conjunction with high voltage solid state devices. The clamping assembly includes a clamp frame having upper and lower clamping plates substantially composed of aluminum and joined together by four dielectric rods composed o... | 01/13/2004 |
| 6542365 | Coolant cooled type semiconductor device A coolant cooled type semiconductor device capable of achieving a superior heat radiation capability is provided, while having a simple structure. While a plurality of semiconductor modules are arranged in such a manner that main surface directions of the... | 04/01/2003 |
| 6489676 | Semiconductor device having an interconnecting post formed on an interposer within a sealing resin A semiconductor device comprises: a semiconductor element; an external terminal used for an external connection; an interposer having the semiconductor element mounted on a first surface thereof and having the external terminal formed on a second surface ... | 12/03/2002 |
| 6324073 | Clamping arrangement for compression-mounted power electronic devices A clamping arrangement is provided for compression mounted power electronic devices that is assembled from component parts to form a clamping module. The clamping module provides suitable clamping force to a power electronic device interposed between two ... | 11/27/2001 |
| 6151201 | Gas-insulated high-voltage semiconductor valve means A gas-insulated semiconductor valve for high voltage power has an elongated valve stack with a plurality of semiconductor elements. The valve stack is provided with electrostatic shields for reducing the stresses on the insulating medium. The shields comp... | 11/21/2000 |
| 5883431 | Device with power semiconductor components A device with power semiconductor components includes, in combination: a stack alternately comprising at least one power semiconductor component and at least one heatsink to dissipate heat and to provide an electrical connection, at least a first system f... | 03/16/1999 |
