Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 7385299 | Stackable integrated circuit package system with multiple interconnect interface A stackable integrated circuit package system is provided forming a first integrated circuit die having an interconnect provided thereon, forming an external interconnect, having an upper tip and a lower tip, from a lead frame, mounting the first integrated circuit ... | 06/10/2008 |
| 7378726 | Stacked packages with interconnecting pins A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die an... | 05/27/2008 |
| 7375418 | Interposer stacking system and method The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while t... | 05/20/2008 |
| 7355271 | Flexible assembly of stacked chips A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( | 04/08/2008 |
| 7355273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. Th... | 04/08/2008 |
| 7335974 | Multi stack packaging chip and method of manufacturing the same A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; ... | 02/26/2008 |
| 7309913 | Stacked semiconductor packages A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semico... | 12/18/2007 |
| 7304375 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 12/04/2007 |
| 7298034 | Multi-chip semiconductor connector assemblies In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die to... | 11/20/2007 |
| 7298038 | Integrated circuit package system including die stacking An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die i... | 11/20/2007 |
| 7298037 | Stacked integrated circuit package-in-package system with recessed spacer A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a subs... | 11/20/2007 |
| 7282791 | Stacked semiconductor device and semiconductor memory module A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless man... | 10/16/2007 |
| 7265441 | Stackable single package and stacked multi-chip assembly A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including co... | 09/04/2007 |
| 7247933 | Thin multiple semiconductor die package A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (1... | 07/24/2007 |
| 7205644 | Memory card structure and manufacturing method thereof A memory card structure comprising a substrate, a plurality of memory chips, some package material and an ultra-thin plastic shell is provided. To fabricate the memory card, a substrate having a first surface and a second surface is provided. The first surface has a... | 04/17/2007 |
| 7187068 | Methods and apparatuses for providing stacked-die devices Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and ass... | 03/06/2007 |
| 7157787 | Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, ... | 01/02/2007 |
| 6927484 | Stack arrangement of a memory module A stack arrangement of discrete components includes a carrier substrate and at least two discrete components, e.g., memory chips. The carrier substrate has line conductor structures and contact pads. Each of the discrete components includes centrally disposed bond p... | 08/09/2005 |
| 6653655 | Integrated semiconductor device including high-voltage interconnections passing through low-voltage regions The integrated semiconductor device includes a first chip of semiconductor material having first, high-voltage, regions at a first high-value voltage; a second chip of semiconductor material having second high-voltage regions connected to the first voltag... | 11/25/2003 |
| 6486528 | Silicon segment programming apparatus and three terminal fuse configuration The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arran... | 11/26/2002 |
| 6255726 | Vertical interconnect process for silicon segments with dielectric isolation An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal inter... | 07/03/2001 |
| 6140699 | Molding for holding heat sinks in a clamped stack In a semiconductor clamped stack, in particular for high-power converters, a plurality of power semiconductor components are arranged alternately together with water-cooled cooling cans in a stack. A clear arrangement of all the components and supplies is... | 10/31/2000 |
| 6134118 | Conductive epoxy flip-chip package and method A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. ... | 10/17/2000 |
| 6124633 | Vertical interconnect process for silicon segments with thermally conductive epoxy preform An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal inter... | 09/26/2000 |
| 6098278 | Method for forming conductive epoxy flip-chip on chip A flip chip on chip method for forming a flip chip assembly including a first flip chip; a second flip chip directly connected to the top of the first flip chip; and electrically conductive epoxy means disposed between the second flip chip and the top of ... | 08/08/2000 |
| 6091142 | Assembly for dissipating heat from a stacked semiconductor package A stacked semiconductor package and a method for assembling the same are disclosed, the stacked semiconductor package including a semiconductor chip having a plurality of wire bonding pads thereon; leads formed in a direction to electrically connect with ... | 07/18/2000 |
| 6084771 | Power electronic module and power electronic device including such modules The invention concerns a power electronic module comprising two individual modules (1) each comprising a power electronic component (5) having a contact face (6) mounted on a metallic face (7) of a substrate (8), power connections (11, 13, 20) a metallic ... | 07/04/2000 |
| 6080596 | Method for forming vertical interconnect process for silicon segments with dielectric isolation A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconn... | 06/27/2000 |
| 5994170 | Silicon segment programming method The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arran... | 11/30/1999 |
| 5936302 | Speaker diaphragm The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arran... | 08/10/1999 |
| 5891761 | Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform A method for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconn... | 04/06/1999 |
| 5837566 | Vertical interconnect process for silicon segments A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of m... | 11/17/1998 |
| 5825090 | High power semiconductor device and method of making same This high-power semiconductor device comprises (a) a disk of refractory metal having flat faces at its opposite sides and (b) two wafers of a semiconductor material having a coefficient of expansion similar to that of the refractory metal, the wafers bein... | 10/20/1998 |
| 5710463 | High-voltage breakover diode A high-voltage breakover diode is proposed, which takes on the function of an ignition voltage distributor of an internal combustion engine having solid-state highvoltage distribution. The high-voltage breakover diode comprises a cascade of breakover diod... | 01/20/1998 |
| 5698895 | Silicon segment programming method and apparatus The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment Once the segments are arrang... | 12/16/1997 |
| 5675180 | Vertical interconnect process for silicon segments A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of m... | 10/07/1997 |
| 5661087 | Vertical interconnect process for silicon segments A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of m... | 08/26/1997 |
| 5657206 | Conductive epoxy flip-chip package and method A method and apparatus for producing a multichip package comprising semiconductor chip and a substrate. The semiconductor chip includes conventional inner bond pads that are rerouted to other areas on the chip to facilitate connection with the substrate. ... | 08/12/1997 |
| 5559371 | Arrangement for premounting disk-shaped cell semiconductors contactable by pressure The invention relates to an arrangement for a preassembled structure of disc cell semiconductors that can be pressure-contacted, in which a loose, stacked module comprising disc cell semiconductors, associated terminal tags and end-side cooling cells and ... | 09/24/1996 |
| 5544412 | Method for coupling a power lead to a bond pad in an electronic module An electronic module and a method for coupling a power lead (32) to a bond pad (28) on a semiconductor die (17) within the electronic module. A clip support (13) having a slot (27) is coupled to a baseplate (11) via an isolation structure (14). The semico... | 08/13/1996 |
