U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Icon_funbox Bizarre Patents

Patent No. 5787895

Kissing Shield

A kissing shield comprised of a thin, flexible membrane and a frame or holder.

Newsletter  PatentStorm News

Make the Most of Our Site

See this month's Top Inventors and Most Cited Patents.

Stay on top of the latest innovations by subscribing to an RSS feed.

Registered users: Manage your profile.

 

Class 257/E25.017 - Apertured devices mounted on one or more rods passed through apertures (EPO)


Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: This subclass is indented under subclass E25.014. This subclass
No. of patents: 6
Last issue date: 03/20/2007


NumberTitleIssue Date
7193307Multi-layer FET array and method of fabricating
A power array includes a plurality of FET power assemblies and each FET power assembly has at least one field effect transistor mounted to a ciruit board. The circuit boards are arranged atop each other. A power supply pin extends through the circuit boards and is c...
03/20/2007
7061094Multilayer printed circuit board including first and second signal traces and a first ground trace
A multilayer printed circuit board (PCB) includes a substrate; a ground layer having edges which define a gap portion, the ground layer being provided on a bottom face of the substrate; and at least two signal traces and provided on a top face of the substrate so as...
06/13/2006
6492720Flat-type semiconductor stack
In a flat-type semiconductor stack formed by alternately stacking flat-type semiconductor devices (1) and heat-radiating elements (2), a projecting pin (7) is provided on a contact surface of at least one flat-type semiconductor device (1) while a positio...
12/10/2002
5309011Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein
To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way...
05/03/1994
5191224Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way...
03/02/1993
4126883Pressure-mounted semiconductive structure
A semiconductive structure comprised of a semiconductive element, feed electrodes and other related components thereof, each provided with an aperture aligned with the aperture of the other elements and a single clamping bolt means positioned through the ...
11/21/1978
 
Sign InRegister
Username  
Password   
forgot password?