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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 7436069 | Semiconductor device, having a through electrode semiconductor module employing thereof and method for manufacturing semiconductor device having a through electrode The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes 103 extending through the silicon substrate 101 is provided. An insulating film 105 is buried within the through hole 103. A ... | 10/14/2008 |
| 7436055 | Packaging method of a plurality of chips stacked on each other and package structure thereof A package structure with a plurality of chips stacked on each other includes a substrate, a first chip and second chip. The substrate has a dielectric layer, a metal layer having a conducting trace area and a shielding area formed on the dielectric layer, and a sold... | 10/14/2008 |
| 7429787 | Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over... | 09/30/2008 |
| 7420262 | Electronic component and semiconductor wafer, and method for producing the same The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the... | 09/02/2008 |
| 7411294 | Display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel. The circuit substrate includes an insulating substrate, a conductive ... | 08/12/2008 |
| 7405472 | Semiconductor device A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission... | 07/29/2008 |
| 7402903 | Semiconductor device Disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a throu... | 07/22/2008 |
| 7388293 | Interposer method of fabricating same, and semiconductor device using the same having two portions with different constructions An interposer to be interposed between a semiconductor chip to be mounted thereon and a packaging board has an interposer portion made of a semiconductor material and an interposer portion provided around the foregoing interposer portion integrally therewith. On bot... | 06/17/2008 |
| 7385281 | Semiconductor integrated circuit device A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a ... | 06/10/2008 |
| 7385299 | Stackable integrated circuit package system with multiple interconnect interface A stackable integrated circuit package system is provided forming a first integrated circuit die having an interconnect provided thereon, forming an external interconnect, having an upper tip and a lower tip, from a lead frame, mounting the first integrated circuit ... | 06/10/2008 |
| 7385282 | Stacked-type chip package structure A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Beside... | 06/10/2008 |
| 7385283 | Three dimensional integrated circuit and method of making the same A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the ... | 06/10/2008 |
| 7378726 | Stacked packages with interconnecting pins A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die an... | 05/27/2008 |
| 7375420 | Large area transducer array A large area transducer array comprising a substrate having a front side and a backside, a plurality of transducers disposed on the front side of the substrate and patterned in the form of a two-dimensional transducer array in the X-Y plane, a plurality of connector... | 05/20/2008 |
| 7375418 | Interposer stacking system and method The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while t... | 05/20/2008 |
| 7372140 | Memory module with different types of multi chip packages In an embodiment, a memory module includes a first group of multi chip packages, including one or more non-volatile memories, and a second group of multi chip packages, including one or more volatile memories, wherein the first and second groups of multi chip packag... | 05/13/2008 |
| 7364945 | Method of mounting an integrated circuit package in an encapsulant cavity An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity. ... | 04/29/2008 |
| 7365418 | Multi-chip structure A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the fi... | 04/29/2008 |
| 7364946 | Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surf... | 04/29/2008 |
| 7358616 | Semiconductor stacked die/wafer configuration and packaging and method thereof A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with... | 04/15/2008 |
| 7358602 | Semiconductor chip, and semiconductor wafer including a variable thickness insulating layer A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface;... | 04/15/2008 |
| 7355274 | Semiconductor package, manufacturing method thereof and IC chip A package may include a lower unit package and an upper unit package. Each of the unit packages may include a circuit substrate having a lower surface and an upper surface. Wire bonding pads may be provided of the lower surface of the circuit substrate, and chip bon... | 04/08/2008 |
| 7355273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. Th... | 04/08/2008 |
| 7354800 | Method of fabricating a stacked integrated circuit package system An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate a... | 04/08/2008 |
| 7355271 | Flexible assembly of stacked chips A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( | 04/08/2008 |
| 7342308 | Component stacking for integrated circuit electronic package Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a compon... | 03/11/2008 |
| 7339275 | Multi-chips semiconductor device assemblies and methods for fabricating the same Multi-chip semiconductor device assemblies and methods for fabricating such assemblies are provided. An exemplary assembly comprises a first chip having a first surface and comprising a plurality of conductive pads disposed at the first surface and a plurality of ci... | 03/04/2008 |
| 7335974 | Multi stack packaging chip and method of manufacturing the same A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; ... | 02/26/2008 |
| 7332736 | Article comprising gated field emission structures with centralized nanowires and method for making the same This invention provides novel methods of fabricating novel gated field emission structures that include aligned nanowire electron emitters (individually or in small groups) localized in central regions within gate apertures. It also provides novel devices using nano... | 02/19/2008 |
| 7321164 | Stack structure with semiconductor chip embedded in carrier A stack structure with semiconductor chips embedded in carriers comprises two carriers stacking together as a whole, at least two semiconductor chips having active surfaces with electrode pads and inactive surfaces corresponding thereto placed in the cavities of the... | 01/22/2008 |
| 7309913 | Stacked semiconductor packages A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semico... | 12/18/2007 |
| 7304375 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 12/04/2007 |
| 7301242 | Programmable system in package Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodi... | 11/27/2007 |
| 7298037 | Stacked integrated circuit package-in-package system with recessed spacer A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a subs... | 11/20/2007 |
| 7298038 | Integrated circuit package system including die stacking An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die i... | 11/20/2007 |
| 7291926 | Multi-chip package structure The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the su... | 11/06/2007 |
| 7285862 | Electronic parts packaging structure in which a semiconductor chip is mounted on a wiring substrate and buried in an insulation film The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where... | 10/23/2007 |
| 7282791 | Stacked semiconductor device and semiconductor memory module A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless man... | 10/16/2007 |
| 7279785 | Stacked die package system A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically con... | 10/09/2007 |
| 7276787 | Silicon chip carrier with conductive through-vias and method for fabricating same A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic... | 10/02/2007 |
