Bizarre Patents
A forehead support apparatus for resting a standing users forehead against a wall above a bathroom commode or urinal or beneath a showerhead.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7432600 | System having semiconductor component with multiple stacked dice A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configu... | 10/07/2008 |
| 7429787 | Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over... | 09/30/2008 |
| 7427810 | Semiconductor device including semiconductor element mounted on another semiconductor element A semiconductor device including a first semiconductor element mounted on a first surface of second semiconductor element, wherein solder balls are formed on the first surface of the second semiconductor element such that the first surface includes an area without s... | 09/23/2008 |
| 7417322 | Multi-chip module with embedded package and method for manufacturing the same A multi-chip module comprises a first package and at least a second package. The first package includes a substrate, at least a first chip, an encapsulant, and a plurality of solder balls. The substrate has an upper surface, a lower surface, and at least an opening.... | 08/26/2008 |
| 7410884 | 3D integrated circuits using thick metal for backside connections and offset bumps Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first ... | 08/12/2008 |
| 7391105 | Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same A unit semiconductor chip and stacked semiconductor package and method of manufacturing with center bonding pads and at least one circuit layer to reduce the length of bonding. The unit semiconductor chip includes a first series of bonding wires connected to a plura... | 06/24/2008 |
| 7391106 | Stack type package A stack type semiconductor package uses rigid, C-shaped guide substrates that hold semiconductor packages stacked in place and which also provide signal pathways between the stacked semiconductors and contact surfaces of the package. The C-shaped guide eliminate sho... | 06/24/2008 |
| 7388294 | Semiconductor components having stacked dice A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as a... | 06/17/2008 |
| 7385299 | Stackable integrated circuit package system with multiple interconnect interface A stackable integrated circuit package system is provided forming a first integrated circuit die having an interconnect provided thereon, forming an external interconnect, having an upper tip and a lower tip, from a lead frame, mounting the first integrated circuit ... | 06/10/2008 |
| 7385282 | Stacked-type chip package structure A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Beside... | 06/10/2008 |
| 7378726 | Stacked packages with interconnecting pins A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die an... | 05/27/2008 |
| 7375418 | Interposer stacking system and method The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC element and the upper shoulder of leads of a lower IC element while t... | 05/20/2008 |
| 7375420 | Large area transducer array A large area transducer array comprising a substrate having a front side and a backside, a plurality of transducers disposed on the front side of the substrate and patterned in the form of a two-dimensional transducer array in the X-Y plane, a plurality of connector... | 05/20/2008 |
| 7372140 | Memory module with different types of multi chip packages In an embodiment, a memory module includes a first group of multi chip packages, including one or more non-volatile memories, and a second group of multi chip packages, including one or more volatile memories, wherein the first and second groups of multi chip packag... | 05/13/2008 |
| 7358115 | Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method fo... | 04/15/2008 |
| 7355271 | Flexible assembly of stacked chips A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip ( | 04/08/2008 |
| 7355264 | Integrated passive devices with high Q inductors The specification describes flip bonded dual substrate inductors wherein a portion of the inductor is constructed on a base IPD substrate, a mating portion of the inductor is constructed on a cover (second) substrate. The cover substrate is then flip bonded to the b... | 04/08/2008 |
| 7355273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. Th... | 04/08/2008 |
| 7348666 | Chip-to-chip trench circuit structure A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conducti... | 03/25/2008 |
| 7335974 | Multi stack packaging chip and method of manufacturing the same A multi stack packaging chip and a method of manufacturing the chip are provided. The method includes forming at least one second circuit element on a first wafer; forming a second wafer having a cavity and a one third circuit element formed opposite to the cavity; ... | 02/26/2008 |
| 7335994 | Semiconductor component having multiple stacked dice A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as a... | 02/26/2008 |
| 7329895 | Dual wavelength detector A sensor comprises two photodiodes sensitive to different wavelengths. The photodiodes or detectors are stacked in a vertical relationship to each other. A bandpass filter is provided to limit the wavelengths of light reaching the detectors. The photodiodes are form... | 02/12/2008 |
| 7307003 | Method of forming a multi-layer semiconductor structure incorporating a processing handle member A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for... | 12/11/2007 |
| 7304375 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 12/04/2007 |
| 7301242 | Programmable system in package Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodi... | 11/27/2007 |
| 7298038 | Integrated circuit package system including die stacking An integrated circuit package system including a leadframe having an aperture provided therein and an integrated circuit package mounted to the leadframe over or under the aperture. A die is mounted within the aperture to the integrated circuit package and the die i... | 11/20/2007 |
| 7298037 | Stacked integrated circuit package-in-package system with recessed spacer A stacked integrated circuit package-in-package system is provided forming a first integrated circuit spacer package including a mold compound with a recess provided therein, stacking the first integrated circuit spacer package on an integrated circuit die on a subs... | 11/20/2007 |
| 7291896 | Voltage droop suppressing active interposer The invention proposes an interposer assembly architecture for noise suppression circuits on the package of a CPU or high power, high frequency VLSI device. In this architecture, charge is stored on dedicated capacitors at a voltage substantially higher than the ope... | 11/06/2007 |
| 7288835 | Integrated circuit package-in-package system An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first inte... | 10/30/2007 |
| 7282791 | Stacked semiconductor device and semiconductor memory module A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless man... | 10/16/2007 |
| 7279785 | Stacked die package system A stacked die package system including forming a bottom package including a bottom substrate and a bottom die mounted and electrically connected under the bottom substrate and forming a top package including a top substrate and a top die mounted and electrically con... | 10/09/2007 |
| 7265441 | Stackable single package and stacked multi-chip assembly A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including co... | 09/04/2007 |
| 7265442 | Stacked package integrated circuit The invention relates to an integrated circuit, electronic device, and method for assembling an integrated circuit package with at least one bottom module with a stacked die package comprising at least two dies within one single mold cap. To allow chip area reductio... | 09/04/2007 |
| 7253530 | Method for producing chip stacks A plurality of interconnect layers are produced on a top side of one or two semiconductor chips, and are mutually isolated from one another in each case by insulation layers that are patterned in such a way that an interconnect layer applied as bridge makes contact ... | 08/07/2007 |
| 7247933 | Thin multiple semiconductor die package A method and apparatus for forming a multiple semiconductor die assembly (200, 300, 400) having a thin profile are presented. The semiconductor die assembly (200, 300, 400) comprises a plurality of die packages (100), with each die package (1... | 07/24/2007 |
| 7247519 | Method for making a semiconductor multi-package module having inverted bump chip carrier second package A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inv... | 07/24/2007 |
| 7221038 | Method of fabricating substrates and substrates obtained by this method Techniques are shown in which substrates having a first layer of a first material and second layer of a second material, wherein the second material is less noble than the first material, is provided by bonding the first and second layers together with an amorphous ... | 05/22/2007 |
| 7205644 | Memory card structure and manufacturing method thereof A memory card structure comprising a substrate, a plurality of memory chips, some package material and an ultra-thin plastic shell is provided. To fabricate the memory card, a substrate having a first surface and a second surface is provided. The first surface has a... | 04/17/2007 |
| 7196427 | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element Two or more semiconductor packages are stacked with an intervening element that is positioned between within an area surrounded by conductive bumps of a bottom surface of the overlying package. Different shapes of the intervening element are used depending upon how ... | 03/27/2007 |
| 7187068 | Methods and apparatuses for providing stacked-die devices Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and ass... | 03/06/2007 |
